2 * fwflash.c - handling the betty flashes
4 * author: hackbard@hackdaworld.org
20 /* bank 0/2 and boootloader addr/size */
21 #define BANK0 0x80000000
22 #define BANK2 0x82000000
23 #define BANK_SIZE 0x00100000
24 #define BOOTLOADER 0x7fffe000
25 #define BL_SIZE 0x00002000
27 /* flash cmd addresses - flash[0-18] <--> arm[1-19]*/
28 #define B0F555 (*((volatile unsigned short *)(BANK0|0xaaa))) // 0x555
29 #define B0F2AA (*((volatile unsigned short *)(BANK0|0x554))) // 0x2aa
30 #define B0F (*((volatile unsigned short *)(BANK0)))
31 #define B2F555 (*((volatile unsigned short *)(BANK2|0xaaa))) // 0x555
32 #define B2F2AA (*((volatile unsigned short *)(BANK2|0x554))) // 0x2aa
33 #define B2F (*((volatile unsigned short *)(BANK2)))
38 #define CMD_CHIP_ERASE 'E'
39 #define CMD_SECTOR_ERASE 'S'
40 #define CMD_CHIP_ID 'I'
48 typedef unsigned char u8;
49 typedef unsigned short u16;
50 typedef unsigned int u32;
56 unsigned long sector_address[19]={
57 0x00000,0x02000,0x03000,0x04000,0x08000,
71 void uart0_send_byte(u8 send);
73 void mmap_init(u8 memtype) {
81 PLLCFG=0x42; // multiplier = 3 (for cclk), dividor = 4 (for f_cco)
82 PLLCON=0x03; // enable and set as clk source for the lpc
87 while(!(PLLSTAT&(1<<10)))
91 void ext_mem_bank_init(void) {
93 BCFG0=0x10000420; // flash 1
94 BCFG1=0x00000c42; // lcd
95 BCFG2=0x10000420; // flash 2
98 void pin_select_init() {
101 * a[19:2] -> address lines
107 void uart0_init(void) {
109 PINSEL0=0x05; // pin select -> tx, rx
110 UART0_FCR=0x07; // enable fifo
111 UART0_LCR=0x83; // set dlab + word length
112 UART0_DLL=0x04; // br: 38400 @ 10/4 mhz
114 UART0_LCR=0x03; // unset dlab
117 void uart0_send_string(char *txbuf) {
124 UART0_THR=txbuf[i++];
125 /* flush if tx buffer maximum reached */
127 while(!(UART0_LSR&(1<<6)))
131 /* flush if \n and \r do not fit in the tx buffer */
133 while(!(UART0_LSR&(1<<6)))
139 /* flush uart0 anyways */
140 while(!(UART0_LSR&(1<<6)))
144 void uart0_send_buf16(u16 *buf,int len) {
150 for(i=0;i<len/2;i++) {
152 while(!(UART0_LSR&(1<<6)))
154 UART0_THR=buf[i]&0xff;
155 UART0_THR=(buf[i]>>8)&0xff;
159 void uart0_send_buf32(u32 *buf,int len) {
165 for(i=0;i<len/4;i++) {
167 while(!(UART0_LSR&(1<<6)))
169 UART0_THR=buf[i]&0xff;
170 UART0_THR=(buf[i]>>8)&0xff;
171 UART0_THR=(buf[i]>>16)&0xff;
172 UART0_THR=(buf[i]>>24)&0xff;
176 void uart0_send_byte(u8 send) {
178 while(!(UART0_LSR&(1<<5)))
184 u8 uart0_get_byte(void) {
188 while(!(UART0_LSR&(1<<0)))
196 void flash_sector_erase(u8 flash,u8 sector) {
203 a18_12=sector_address[sector]<<1;
205 if((flash!='0')&(flash!='2'))
216 *((volatile u16 *)(base|a18_12))=0x30;
225 *((volatile u16 *)(base|a18_12))=0x30;
234 void flash_chip_erase(u8 bank) {
236 if((bank!='0')&(bank!='2'))
257 void unlock_bypass(u8 bank) {
259 if((bank!='0')&(bank!='2'))
274 void unlock_bypass_reset(u8 bank) {
276 if((bank!='0')&(bank!='2'))
289 void flash_write(u32 addr,u16 data) {
291 *((volatile unsigned short *)addr)=0xa0;
292 *((volatile unsigned short *)addr)=data;
295 void receive_data_and_write_to_flash(u32 addr,u32 datalen) {
303 /* which bank to program */
312 /* receive and write data */
314 for(i=0;i<datalen/2;i++) {
315 byte=uart0_get_byte();
318 byte=uart0_get_byte();
321 *((unsigned volatile short *)addr)=0xa0;
322 *((unsigned volatile short *)addr)=data;
327 unlock_bypass_reset(bank);
330 uart0_send_byte(cksm);
341 u32 i,addrlen,datalen,addr;
347 /* memory mapping of interrupt vectors to static ram */
349 //mmap_init(MMAP_RAM);
351 /* pll initialization */
354 /* uart initialization */
357 /* external memory init */
360 /* pin select init */
363 /* begin the main loop */
369 cmd=uart0_get_byte();
376 case CMD_SECTOR_ERASE:
400 /* receive (only if there is) more data from uart0 */
402 for(i=0;i<addrlen;i++) {
403 txrx=uart0_get_byte();
404 addr|=(txrx<<((addrlen-i-1)*8));
407 for(i=0;i<datalen;i++)
408 buf[i]=uart0_get_byte();
410 /* process the cmd */
412 case CMD_SECTOR_ERASE:
413 flash_sector_erase(buf[0],buf[1]);
416 /* data length to read */
417 datalen=buf[0]<<24|buf[1]<<16|buf[2]<<8|buf[3];
418 /* check addr and datalen */
419 if((addr>=BANK0)&(addr+datalen<=BANK0+BANK_SIZE))
420 uart0_send_buf16((u16 *)addr,datalen);
421 if((addr>=BANK2)&(addr+datalen<=BANK2+BANK_SIZE))
422 uart0_send_buf16((u16 *)addr,datalen);
423 if((addr>=BOOTLOADER)&(addr+datalen<=BOOTLOADER+BL_SIZE))
424 uart0_send_buf32((u32 *)addr,datalen);
428 datalen=buf[0]<<24|buf[1]<<16|buf[2]<<8|buf[3];
429 /* check addr and data len */
430 if(((addr>=BANK0)&(addr+datalen<=BANK0+BANK_SIZE))|
431 ((addr>=BANK2)&(addr+datalen<=BANK2+BANK_SIZE)))
432 receive_data_and_write_to_flash(addr,datalen);
435 flash_chip_erase(buf[0]);
442 data=*((u16 *)BANK0);
443 uart0_send_buf16(&data,2);
444 data=*((u16 *)(BANK0|0x200));
445 uart0_send_buf16(&data,2);
447 else if(buf[0]=='2') {
451 data=*((u16 *)BANK2);
452 uart0_send_buf16(&data,2);
453 data=*((u16 *)(BANK2|0x200));
454 uart0_send_buf16(&data,2);