2 * system.c - misc system specific stuff
4 * author: hackbard@hackdaworld.org
17 PLLCFG=0x42; // multiplier = 3 (for cclk), dividor = 4 (for f_cco)
18 PLLCON=0x03; // enable and set as clk source for the lpc
25 while(!(PLLSTAT&(1<<10)))
29 void ext_mem_init(void) {
32 * flash at bank0 and bank:
34 * idle clocks between rad & write: 0+1
35 * length of read access: 1+3
36 * bls lines high during write access
37 * length of write access: 0+extra
38 * no write protect, no burst-rom
43 BCFG0=0x10000420; // bank 0
44 BCFG2=0x10000420; // bank 2
49 * idle clocks between rad & write: 2+1
50 * length of read access: 2+3
51 * bls lines low during write access
52 * length of write access: 1+extra
53 * no write protect, no burst-rom
58 BCFG1=0x00000c42; // bank 1
75 * no special function yet!
84 * orig fw -> d 6 0 4 1 d 4
85 * 1101 0110 0000 0100 0001 1101 0100
87 * this fw -> d e 0 4 9 d 4
88 * 1101 1110 0000 0100 1001 1101 0100
92 * - p3.26 should be chip select for ext mem bank 1
93 * - p3.0 should be address line 0
95 * explanation: maybe bcfg1 config implies these settings
107 * out: p2.18 - p2.24 (+ pull high)
108 * in: p0.30, p0.{27,28}, p3.{20,21}, p0.22, p0.13
112 // nothing to do for inputs (default: 0x00000000)
113 IODIR2=((1<<18)|(1<<19)|(1<<20)|(1<<21)|(1<<22)|(1<<23)|(1<<24));
114 IOSET2=((1<<18)|(1<<19)|(1<<20)|(1<<21)|(1<<22)|(1<<23)|(1<<24));
117 void mmap_init(u8 memtype) {
122 void pause(u32 cnt) {
126 asm volatile ("nop");