4 * author: hackbard@hackdaworld.org
7 * - switch on board power (done)
8 * - allow high speed bulk usb transfer
13 /* constant definitions */
19 /* type definitions */
20 typedef unsigned char u8;
21 typedef unsigned short u16;
22 typedef unsigned int u32;
28 /* general configuration */
29 xdata at 0xe600 volatile u8 CPUCS;
30 xdata at 0xe601 volatile u8 IFCONFIG;
32 /* endpoint configuration */
33 xdata at 0xe604 volatile u8 FIFORESET;
34 xdata at 0xe60b volatile u8 REVCTL;
35 xdata at 0xe610 volatile u8 EP1OUTCFG;
36 xdata at 0xe611 volatile u8 EP1INCFG;
37 xdata at 0xe612 volatile u8 EP2CFG;
38 xdata at 0xe613 volatile u8 EP4CFG;
39 xdata at 0xe614 volatile u8 EP6CFG;
40 xdata at 0xe615 volatile u8 EP8CFG;
41 xdata at 0xe618 volatile u8 EP2FIFOCFG;
42 xdata at 0xe619 volatile u8 EP4FIFOCFG;
43 xdata at 0xe61a volatile u8 EP6FIFOCFG;
44 xdata at 0xe61b volatile u8 EP8FIFOCFG;
45 xdata at 0xe620 volatile u8 EP2AUTOINLENH;
46 xdata at 0xe621 volatile u8 EP2AUTOINLENL;
47 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
48 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
50 /* endpoint control/status */
51 xdata at 0xe6a1 volatile u8 EP1OUTCS;
52 xdata at 0xe6a2 volatile u8 EP1INCS;
53 xdata at 0xe68d volatile u16 EP1OUTBC;
54 xdata at 0xe68f volatile u16 EP1INBC;
59 /* access to endpoint buffers */
60 xdata at 0xe780 volatile u8 EP1OUTBUF[64];
61 xdata at 0xe7c0 volatile u8 EP1INBUF[64];
63 /* special funtion registers */
67 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
68 * and some others (p. 438).
69 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
70 #define SYNCDELAY _asm \
71 nop; nop; nop; nop; nop; nop; nop; nop; \
72 nop; nop; nop; nop; nop; nop; nop; nop; \
77 /* pin 7 of port d connected to mosfet gate controlling the board power
79 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
82 /* configure pin 7 of port d as output */
90 /* toggle high/low state of the mosfet gate */
103 /* pin 5 of port d disables tdi -> tdo forward */
108 * tdi - pin 0 (input)
109 * tdo - pin 2 (output)
110 * tms - pin 3 (output)
111 * tck - pin 4 (output)
113 OED|=((1<<2)|(1<<3)|(1<<4));
120 /* cpu initialization: (0x10)
122 * - none inverted signal
131 void slave_fifo_init() {
133 /* initialization of the slave fifo, used by external logic (the fpga)
134 * to do usb communication with the host */
136 /* set bit 0 and 1 - fifo slave config */
144 /* p. 180: must be set to 1 */
145 REVCTL|=((1<<0)|(1<<1));
148 /* 8 bit fifo to all endpoints
150 * ('or' of all these bits define port d functionality)
161 /* default indexed flag configuration:
163 * flag a: programmable level
167 * todo: -> fixed configuration
170 /* endpoint configuration:
172 * ep2: bulk out 4x512
175 * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
176 * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
188 FIFORESET=0x80; /* nak all transfers */
190 FIFORESET=0x02; /* reset ep2 */
192 FIFORESET=0x06; /* reset ep6 */
194 FIFORESET=0x00; /* restore normal operation */
197 /* auto in/out, no cpu interaction! auto in len = 512 */
202 EP6AUTOINLENH=(1<<1);
211 /* initialize endpoint 1
213 * used for jtag & control
216 /* endpoint 1 configuration:
218 * default (valid, bulk) fits!
221 /* arm ep1out, clear ep1out and ep1in stall bit */
233 /* power init & power on */
237 /* slave fifo init */
248 /* initialize the fx2 */
251 /* jtag by polling ep1 */
253 if(!(EP1OUTCS&BUSY)) {
259 if(!(EP1INCS&BUSY)) {