4 * author: hackbard@hackdaworld.org
7 * - switch on board power (done)
8 * - allow high speed bulk usb transfer
13 /* constant definitions */
19 /* type definitions */
20 typedef unsigned char u8;
21 typedef unsigned short u16;
22 typedef unsigned int u32;
28 /* general configuration */
29 xdata at 0xe600 volatile u8 CPUCS;
30 xdata at 0xe601 volatile u8 IFCONFIG;
32 /* endpoint configuration */
33 xdata at 0xe604 volatile u8 FIFORESET;
34 xdata at 0xe60b volatile u8 REVCTL;
35 xdata at 0xe612 volatile u8 EP2CFG;
36 xdata at 0xe613 volatile u8 EP4CFG;
37 xdata at 0xe614 volatile u8 EP6CFG;
38 xdata at 0xe615 volatile u8 EP8CFG;
39 xdata at 0xe618 volatile u8 EP2FIFOCFG;
40 xdata at 0xe619 volatile u8 EP4FIFOCFG;
41 xdata at 0xe61a volatile u8 EP6FIFOCFG;
42 xdata at 0xe61b volatile u8 EP8FIFOCFG;
43 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
44 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
46 /* special funtion registers */
50 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
51 * and some others (p. 438).
52 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
53 #define SYNCDELAY _asm \
54 nop; nop; nop; nop; nop; nop; nop; nop; \
55 nop; nop; nop; nop; nop; nop; nop; nop; \
60 /* pin 7 of port d connected to mosfet gate controlling the board power
62 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
65 /* configure pin 7 of port d as output */
72 /* toggle high/low state of the mosfet gate */
83 /* cpu initialization: (0x10)
85 * - none inverted signal
94 void slave_fifo_init() {
96 /* initialization of the slave fifo, used by external logic (the fpga)
97 * to do usb communication with the host */
99 /* set bit 0 and 1 - fifo slave config */
107 /* p. 180: must be set to 1 */
108 REVCTL|=((1<<0)|(1<<1));
111 /* 8 bit fifo to all endpoints
113 * ('or' of all these bits define port d functionality)
124 /* default indexed flag configuration:
126 * flag a: programmable level
130 * todo: -> fixed configuration
133 /* endpoint configuration:
136 * ep6: bulk out 4x512
138 * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
139 * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
140 * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
152 FIFORESET=0x80; /* nak all transfers */
154 FIFORESET=0x02; /* reset ep2 */
156 FIFORESET=0x06; /* reset ep6 */
158 FIFORESET=0x00; /* restore normal operation */
161 /* auto in/out, no cpu interaction! auto in len = 512 */
166 EP6AUTOINLENH=(1<<1);
175 /* initialize endpoint 1
177 * used for jtag & control
180 /* endpoint 1 configuration:
182 * default (valid, bulk) fits!
192 /* power init & power on */
196 /* slave fifo init */
205 /* initialize the fx2 */