1 ;***************************************************************************
\r
2 ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
\r
5 ;* File Name : "m104def.inc"
\r
6 ;* Title : Register/Bit Definitions for the ATmega104
\r
7 ;* Date : January 25th, 2000
\r
9 ;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
\r
10 ;* Support fax : +47 72 88 43 99 (ATMEL Norway)
\r
11 ;* Support E-mail : support@atmel.no
\r
12 ;* Target MCU : ATmega104
\r
15 ;* When including this file in the assembly program file, all I/O register
\r
16 ;* names and I/O register bit names appearing in the data book can be used.
\r
17 ;* In addition, the six registers forming the three data pointers X, Y and
\r
18 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
\r
19 ;* SRAM is also defined
\r
21 ;* The Register names are represented by their hexadecimal address.
\r
23 ;* The Register Bit names are represented by their bit number (0-7).
\r
25 ;* Please observe the difference in using the bit names with instructions
\r
26 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
\r
27 ;* (skip if bit in register set/cleared). The following example illustrates
\r
30 ;* in r16,PORTB ;read PORTB latch
\r
31 ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
\r
32 ;* out PORTB,r16 ;output to PORTB
\r
34 ;* in r16,TIFR ;read the Timer Interrupt Flag Register
\r
35 ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
\r
36 ;* rjmp TOV0_is_set ;jump if set
\r
37 ;* ... ;otherwise do something else
\r
38 ;***************************************************************************
\r
39 ;$Author: hackbard $
\r
40 ;$Date: 2003-12-06 01:15:10 $
\r
42 ;$Source: /chroot/cvs/my-code/atmel/include/m104def.inc,v $
\r
44 ;**** Specify Device ****
\r
48 ;*****************************************************************************
\r
49 ; I/O Register Definitions
\r
50 ;*****************************************************************************
\r
52 ;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
\r
99 .equ SPMCR = $68 ; old name for SPMCSR
\r
108 ;**** I/O Register Definitions ($3F-$00) ****
\r
116 .equ GIMSK = $39 ; old name for EIMSK
\r
117 .equ GICR = $39 ; old name for EIMSK
\r
119 .equ GIFR = $38 ; old name for EIFR
\r
141 .equ OCDR = $22 ; New
\r
143 .equ SFIOR = $20 ; New
\r
155 .equ DDRC = $14 ; New
\r
156 .equ PINC = $13 ; New
\r
178 ;*****************************************************************************
\r
180 ;*****************************************************************************
\r
182 ;**** MCU Control ****
\r
183 .equ SRE = 7 ; MCUCR
\r
192 .equ JTD = 7 ; MCUCSR
\r
199 .equ SRL2 =6 ; XMCRA
\r
206 .equ XMBK = 7 ; XMCRB
\r
211 .equ SPMIE =7 ; SPMCSR
\r
212 .equ ASB =6 ; backwards compatiblity
\r
213 .equ ASRE =4 ; backwards compatiblity
\r
221 .equ IDRD = 7 ; OCDR
\r
230 .equ XDIVEN = 7 ; XDIV
\r
239 .equ TSM = 7 ; SFIOR
\r
249 ;**** Analog to Digital Converter ****
\r
250 .equ ADEN = 7 ; ADCSR
\r
259 .equ REFS1 =7 ; ADMUX
\r
268 ;**** Analog Comparator ****
\r
269 .equ ACD = 7 ; ACSR
\r
279 ;**** External Interrupts ****
\r
280 .equ INT7 = 7 ; EIMSK
\r
289 .equ INTF7 = 7 ; EIFR
\r
298 .equ ISC71 = 7 ; EICRB
\r
307 .equ ISC31 = 7 ; EICRA
\r
316 ;**** Timer Interrupts ****
\r
317 .equ OCIE2 = 7 ; TIMSK
\r
326 .equ TICIE3 = 5 ; ETIMSK
\r
333 .equ OCF2 = 7 ; TIFR
\r
342 .equ ICF3 = 5 ; ETIFR
\r
349 ;**** Asynchronous Timer ****
\r
350 .equ AS0 = 3 ; ASSR
\r
356 .equ FOC0 = 7 ; TCCR0
\r
366 .equ COM1A1 = 7 ; TCCR1A
\r
372 .equ PWM11 = 1 ; OBSOLETE! Use WGM11
\r
373 .equ PWM10 = 0 ; OBSOLETE! Use WGM10
\r
377 .equ ICNC1 = 7 ; TCCR1B
\r
379 .equ CTC11 = 4 ; OBSOLETE! Use WGM13
\r
380 .equ CTC10 = 3 ; OBSOLETE! Use WGM12
\r
387 .equ FOC1A = 7 ; TCCR1C
\r
392 .equ FOC2 = 7 ; TCCR2
\r
402 .equ COM3A1 = 7 ; TCCR3A
\r
408 .equ PWM31 = 1 ; OBSOLETE! Use WGM31
\r
409 .equ PWM30 = 0 ; OBSOLETE! Use WGM30
\r
413 .equ ICNC3 = 7 ; TCCR3B
\r
415 .equ CTC31 = 4 ; OBSOLETE! Use WGM33
\r
416 .equ CTC30 = 3 ; OBSOLETE! Use WGM32
\r
423 .equ FOC3A = 7 ; TCCR3C
\r
427 ;**** Watchdog Timer ****
\r
428 .equ WDCE = 4 ; WDTCR
\r
429 .equ WDTOE = 4 ; For Mega103 compability
\r
435 ;**** EEPROM Control Register ****
\r
436 .equ EERIE = 3 ; EECR
\r
441 ;**** USART 0 and USART 1 ****
\r
442 .equ RXC = 7 ; (UCSRA0/1)
\r
447 .equ PE = 2 ; OBSOLETED!
\r
451 .equ RXC0 = 7 ; (UCSR0A)
\r
460 .equ RXC1 = 7 ; (UCSR1A)
\r
469 .equ RXCIE = 7 ; (UCSRB0/1)
\r
478 .equ RXCIE0 = 7 ; (UCSR0B)
\r
487 .equ RXCIE1 = 7 ; (UCSR1B)
\r
496 .equ UMSEL = 6 ; (UCSRC0/1)
\r
504 .equ UMSEL0 = 6 ; (UCSR0C)
\r
512 .equ UMSEL1 = 6 ; (UCSR1C)
\r
522 .equ SPIE = 7 ; SPCR
\r
531 .equ SPIF = 7 ; SPSR
\r
544 .equ TWS7 = 7 ; TWSR
\r
549 .equ TWGCE = 0 ; TWAR
\r
553 .equ PA7 = 7 ; PORTA
\r
570 .equ DDA7 = 7 ; DDRA
\r
579 .equ PINA7 = 7 ; PINA
\r
589 .equ PB7 = 7 ; PORTB
\r
606 .equ DDB7 = 7 ; DDRB
\r
615 .equ PINB7 = 7 ; PINB
\r
625 .equ PC7 = 7 ; PORTC
\r
642 .equ DDC7 = 7 ; DDRC
\r
651 .equ PINC7 = 7 ; PINC
\r
661 .equ PD7 = 7 ; PORTD
\r
678 .equ DDD7 = 7 ; DDRD
\r
687 .equ PIND7 = 7 ; PIND
\r
697 .equ PE7 = 7 ; PORTE
\r
705 .equ PORTE7 = 7 ; PORTE
\r
714 .equ DDE7 = 7 ; DDRE
\r
723 .equ PINE7 = 7 ; PINE
\r
733 .equ PF7 = 7 ; PORTF
\r
750 .equ DDF7 = 7 ; DDRF
\r
759 .equ PINF7 = 7 ; PINF
\r
769 .equ PG4 = 4 ; PORTG
\r
775 .equ DDG4 = 4 ; DDRG
\r
781 .equ PING4 = 4 ; PING
\r
788 ;*****************************************************************************
\r
789 ; CPU Register Declarations
\r
790 ;*****************************************************************************
\r
792 .def XL = r26 ; X pointer low
\r
793 .def XH = r27 ; X pointer high
\r
794 .def YL = r28 ; Y pointer low
\r
795 .def YH = r29 ; Y pointer high
\r
796 .def ZL = r30 ; Z pointer low
\r
797 .def ZH = r31 ; Z pointer high
\r
800 ;*****************************************************************************
\r
801 ; Data Memory Declarations
\r
802 ;*****************************************************************************
\r
804 .equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.
\r
805 .equ EEPROMEND = $0fff ; Highest EEPROM address.
\r
807 ;*****************************************************************************
\r
808 ; Program Memory Declarations
\r
809 ;*****************************************************************************
\r
811 .equ FLASHEND = $FFFF ; Highest program memory (flash) address
\r
812 ; (When addressed as 16 bit words)
\r
814 ;**** Boot Vectors ****
\r
816 ; /--\/--\/--\/--\
\r
817 .equ SMALLBOOTSTART = 0b1111111000000000 ; ($FE00) Smallest boot block is 512W
\r
818 .equ SECONDBOOTSTART = 0b1111110000000000 ; ($FC00) 2'nd boot block size is 1KW
\r
819 .equ THIRDBOOTSTART = 0b1111100000000000 ; ($F800) Third boot block size is 2KW
\r
820 .equ LARGEBOOTSTART = 0b1111000000000000 ; ($F000) Largest boot block is 4KW
\r
823 ;**** Page Size ****
\r
824 .equ PAGESIZE = 128 ; Number of WORDS in a page
\r
827 ;**** Interrupt Vectors ****
\r
828 .equ INT0addr = $002 ; External Interrupt0 Vector Address
\r
829 .equ INT1addr = $004 ; External Interrupt1 Vector Address
\r
830 .equ INT2addr = $006 ; External Interrupt2 Vector Address
\r
831 .equ INT3addr = $008 ; External Interrupt3 Vector Address
\r
832 .equ INT4addr = $00a ; External Interrupt4 Vector Address
\r
833 .equ INT5addr = $00c ; External Interrupt5 Vector Address
\r
834 .equ INT6addr = $00e ; External Interrupt6 Vector Address
\r
835 .equ INT7addr = $010 ; External Interrupt7 Vector Address
\r
836 .equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address
\r
837 .equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address
\r
838 .equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address
\r
839 .equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address
\r
840 .equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address
\r
841 .equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address
\r
842 .equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address
\r
843 .equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address
\r
844 .equ SPIaddr = $022 ; SPI Interrupt Vector Address
\r
845 .equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address
\r
846 .equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address
\r
847 .equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address
\r
848 .equ ADCCaddr = $02a ; ADC Conversion Complete Handle
\r
849 .equ ERDYaddr = $02c ; EEPROM Write Complete Handle
\r
850 .equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address
\r
852 .equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address
\r
853 .equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address
\r
854 .equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address
\r
855 .equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address
\r
856 .equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address
\r
857 .equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address
\r
858 .equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address
\r
859 .equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address
\r
860 .equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address
\r
861 .equ TWIaddr = $042 ; TWI Interrupt Vector Address
\r
862 .equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address
\r
865 ;**** End of File ****
\r