1 ;***************************************************************************
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2 ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 ;* File Name : "m128def.inc"
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6 ;* Title : Register/Bit Definitions for the ATmega128
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9 ;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
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10 ;* Support fax : +47 72 88 43 99 (ATMEL Norway)
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11 ;* Support E-mail : avr@atmel.no
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12 ;* Target MCU : ATmega128
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15 ;* When including this file in the assembly program file, all I/O register
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16 ;* names and I/O register bit names appearing in the data book can be used.
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17 ;* In addition, the six registers forming the three data pointers X, Y and
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18 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 ;* SRAM is also defined
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21 ;* The Register names are represented by their hexadecimal address.
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23 ;* The Register Bit names are represented by their bit number (0-7).
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25 ;* Please observe the difference in using the bit names with instructions
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26 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 ;* (skip if bit in register set/cleared). The following example illustrates
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30 ;* in r16,PORTB ;read PORTB latch
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31 ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 ;* out PORTB,r16 ;output to PORTB
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34 ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 ;* rjmp TOV0_is_set ;jump if set
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37 ;* ... ;otherwise do something else
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38 ;***************************************************************************
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40 ;**** Specify Device ****
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43 ;*****************************************************************************
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44 ; I/O Register Definitions
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45 ;*****************************************************************************
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47 ;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
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84 .equ SPMCR = $68 ; old name for SPMCSR
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91 ;**** I/O Register Definitions ($3F-$00) ****
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99 .equ GIMSK = $39 ; old name for EIMSK
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100 .equ GICR = $39 ; old name for EIMSK
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102 .equ GIFR = $38 ; old name for EIFR
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124 .equ OCDR = $22 ; New
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126 .equ SFIOR = $20 ; New
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138 .equ DDRC = $14 ; New
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139 .equ PINC = $13 ; New
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161 ;*****************************************************************************
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163 ;*****************************************************************************
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165 ;**** MCU Control ****
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166 .equ SRE = 7 ; MCUCR
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175 .equ JTD = 7 ; MCUCSR
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182 .equ SRL2 =6 ; XMCRA
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189 .equ XMBK = 7 ; XMCRB
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194 .equ SPMIE =7 ; SPMCSR
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195 .equ ASB =6 ; backwards compatiblity
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196 .equ ASRE =4 ; backwards compatiblity
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204 .equ IDRD = 7 ; OCDR
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213 .equ XDIVEN = 7 ; XDIV
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222 .equ TSM = 7 ; SFIOR
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232 ;**** Analog to Digital Converter ****
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233 .equ ADEN = 7 ; ADCSR
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242 .equ REFS1 =7 ; ADMUX
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251 ;**** Analog Comparator ****
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252 .equ ACD = 7 ; ACSR
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262 ;**** External Interrupts ****
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263 .equ INT7 = 7 ; EIMSK
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272 .equ INTF7 = 7 ; EIFR
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281 .equ ISC71 = 7 ; EICRB
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290 .equ ISC31 = 7 ; EICRA
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299 ;**** Timer Interrupts ****
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300 .equ OCIE2 = 7 ; TIMSK
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309 .equ TICIE3 = 5 ; ETIMSK
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316 .equ OCF2 = 7 ; TIFR
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325 .equ ICF3 = 5 ; ETIFR
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332 ;**** Asynchronous Timer ****
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333 .equ AS0 = 3 ; ASSR
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339 .equ FOC0 = 7 ; TCCR0
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349 .equ COM1A1 = 7 ; TCCR1A
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355 .equ PWM11 = 1 ; OBSOLETE! Use WGM11
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356 .equ PWM10 = 0 ; OBSOLETE! Use WGM10
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360 .equ ICNC1 = 7 ; TCCR1B
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362 .equ CTC11 = 4 ; OBSOLETE! Use WGM13
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363 .equ CTC10 = 3 ; OBSOLETE! Use WGM12
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370 .equ FOC1A = 7 ; TCCR1C
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375 .equ FOC2 = 7 ; TCCR2
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385 .equ COM3A1 = 7 ; TCCR3A
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391 .equ PWM31 = 1 ; OBSOLETE! Use WGM31
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392 .equ PWM30 = 0 ; OBSOLETE! Use WGM30
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396 .equ ICNC3 = 7 ; TCCR3B
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398 .equ CTC31 = 4 ; OBSOLETE! Use WGM33
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399 .equ CTC30 = 3 ; OBSOLETE! Use WGM32
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406 .equ FOC3A = 7 ; TCCR3C
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410 ;**** Watchdog Timer ****
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411 .equ WDCE = 4 ; WDTCR
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412 .equ WDTOE = 4 ; For Mega103 compability
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418 ;**** EEPROM Control Register ****
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419 .equ EERIE = 3 ; EECR
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424 ;**** USART 0 and USART 1 ****
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425 .equ RXC = 7 ; (UCSRA0/1)
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430 .equ PE = 2 ; OBSOLETED!
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434 .equ RXC0 = 7 ; (UCSR0A)
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443 .equ RXC1 = 7 ; (UCSR1A)
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452 .equ RXCIE = 7 ; (UCSRB0/1)
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461 .equ RXCIE0 = 7 ; (UCSR0B)
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470 .equ RXCIE1 = 7 ; (UCSR1B)
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479 .equ UMSEL = 6 ; (UCSRC0/1)
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487 .equ UMSEL0 = 6 ; (UCSR0C)
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495 .equ UMSEL1 = 6 ; (UCSR1C)
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505 .equ SPIE = 7 ; SPCR
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514 .equ SPIF = 7 ; SPSR
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519 .equ TWINT = 7 ;TWCR
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527 .equ TWS7 = 7 ; TWSR
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542 .equ TWGCE = 0 ; TWAR
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546 .equ PA7 = 7 ; PORTA
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563 .equ DDA7 = 7 ; DDRA
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572 .equ PINA7 = 7 ; PINA
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582 .equ PB7 = 7 ; PORTB
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599 .equ DDB7 = 7 ; DDRB
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608 .equ PINB7 = 7 ; PINB
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618 .equ PC7 = 7 ; PORTC
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635 .equ DDC7 = 7 ; DDRC
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644 .equ PINC7 = 7 ; PINC
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654 .equ PD7 = 7 ; PORTD
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671 .equ DDD7 = 7 ; DDRD
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680 .equ PIND7 = 7 ; PIND
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690 .equ PE7 = 7 ; PORTE
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698 .equ PORTE7 = 7 ; PORTE
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707 .equ DDE7 = 7 ; DDRE
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716 .equ PINE7 = 7 ; PINE
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726 .equ PF7 = 7 ; PORTF
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743 .equ DDF7 = 7 ; DDRF
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752 .equ PINF7 = 7 ; PINF
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762 .equ PG4 = 4 ; PORTG
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768 .equ DDG4 = 4 ; DDRG
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774 .equ PING4 = 4 ; PING
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781 ;*****************************************************************************
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782 ; CPU Register Declarations
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783 ;*****************************************************************************
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785 .def XL = r26 ; X pointer low
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786 .def XH = r27 ; X pointer high
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787 .def YL = r28 ; Y pointer low
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788 .def YH = r29 ; Y pointer high
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789 .def ZL = r30 ; Z pointer low
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790 .def ZH = r31 ; Z pointer high
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793 ;*****************************************************************************
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794 ; Data Memory Declarations
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795 ;*****************************************************************************
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797 .equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.
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798 .equ EEPROMEND = $0fff ; Highest EEPROM address.
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800 ;*****************************************************************************
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801 ; Program Memory Declarations
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802 ;*****************************************************************************
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804 .equ FLASHEND = $FFFF ; Highest program memory (flash) address
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805 ; (When addressed as 16 bit words)
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807 ;**** Boot Vectors ****
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809 ; /--\/--\/--\/--\
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810 .equ SMALLBOOTSTART = 0b1111111000000000 ; ($FE00) Smallest boot block is 512W
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811 .equ SECONDBOOTSTART = 0b1111110000000000 ; ($FC00) 2'nd boot block size is 1KW
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812 .equ THIRDBOOTSTART = 0b1111100000000000 ; ($F800) Third boot block size is 2KW
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813 .equ LARGEBOOTSTART = 0b1111000000000000 ; ($F000) Largest boot block is 4KW
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816 ;**** Page Size ****
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817 .equ PAGESIZE = 128 ; Number of WORDS in a page
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820 ;**** Interrupt Vectors ****
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821 .equ INT0addr = $002 ; External Interrupt0 Vector Address
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822 .equ INT1addr = $004 ; External Interrupt1 Vector Address
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823 .equ INT2addr = $006 ; External Interrupt2 Vector Address
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824 .equ INT3addr = $008 ; External Interrupt3 Vector Address
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825 .equ INT4addr = $00a ; External Interrupt4 Vector Address
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826 .equ INT5addr = $00c ; External Interrupt5 Vector Address
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827 .equ INT6addr = $00e ; External Interrupt6 Vector Address
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828 .equ INT7addr = $010 ; External Interrupt7 Vector Address
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829 .equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address
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830 .equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address
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831 .equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address
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832 .equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address
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833 .equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address
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834 .equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address
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835 .equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address
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836 .equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address
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837 .equ SPIaddr = $022 ; SPI Interrupt Vector Address
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838 .equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address
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839 .equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address
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840 .equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address
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841 .equ ADCCaddr = $02a ; ADC Conversion Complete Handle
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842 .equ ERDYaddr = $02c ; EEPROM Write Complete Handle
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843 .equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address
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845 .equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address
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846 .equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address
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847 .equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address
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848 .equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address
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849 .equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address
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850 .equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address
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851 .equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address
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852 .equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address
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853 .equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address
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854 .equ TWIaddr = $042 ; TWI Interrupt Vector Address
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855 .equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address
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858 ;**** End of File ****
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