1 ;***************************************************************************
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2 ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 ;* File Name :"m162def.inc"
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6 ;* Title :Register/Bit Definitions for the ATmega162
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9 ;* Support telephone :+47 72 88 43 88 (ATMEL Norway)
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10 ;* Support fax :+47 72 88 43 99 (ATMEL Norway)
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11 ;* Support E-mail :avr@atmel.no
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12 ;* Target MCU :ATmega162
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15 ;* When including this file in the assembly program file, all I/O register
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16 ;* names and I/O register bit names appearing in the data book can be used.
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17 ;* In addition, the six registers forming the three data pointers X, Y and
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18 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 ;* SRAM is also defined
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21 ;* The Register names are represented by their hexadecimal address.
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23 ;* The Register Bit names are represented by their bit number (0-7).
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25 ;* Please observe the difference in using the bit names with instructions
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26 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 ;* (skip if bit in register set/cleared). The following example illustrates
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30 ;* in r16,PORTB ;read PORTB latch
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31 ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 ;* out PORTB,r16 ;output to PORTB
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34 ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 ;* rjmp TOV0_is_set ;jump if set
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37 ;* ... ;otherwise do something else
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38 ;***************************************************************************
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40 ;***** Specify Device
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43 ;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
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44 ;**** Not available in Mega162 compatibility mode ****
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61 ;***** I/O Register Definitions
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65 .equ UCSR1C =$3c ; Note! UCSR1C equals UBRR1H
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66 .equ UBRR1H =$3c ; Note! UCSR1C equals UBRR1H
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69 .equ GICR =$3b ; new name for GIMSK
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76 .equ MCUSR =$34 ; For compatibility,
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77 .equ MCUCSR =$34 ; keep both names until further
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97 .equ UBRRHI =$20 ; Old ATmega161
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98 .equ UCSR0C =$20 ; Note! UCSR0C equals UBRR0H
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99 .equ UBRR0H =$20 ; Note! UCSR0C equals UBRR0H
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120 .equ UDR =$0c ;for compatibility with s8515
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122 .equ USR =$0b ;for compatibility with s8515
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124 .equ UCR =$0a ;for compatibility with s8515
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125 .equ UBRR0 =$09 ;Old mega161
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127 .equ UBRR =$09 ;for compatibility with s8515
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132 .equ OSCCAL =$04 ; New
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136 .equ UBRR1 =$00 ;Old mega161
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139 ;***** Bit Definitions
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204 .equ IVSEL =1 ; Interrupt vector select
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205 .equ IVCE =0 ; Interrupt vector change enable
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258 .equ SRW =6 ;for compatibility with s8515
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261 .equ SM =4 ;for compatibility with s8515
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280 .equ PWM0 =6 ; OBSOLETE! Use WGM00
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284 .equ CTC0 =3 ; OBSOLETE! Use WGM01
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291 .equ XMBK = 6 ; Added for Mega162
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297 .equ PSR10 = 0 ; Note: The prescaler reset is shared
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298 ; between timer 0 and 1.
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309 .equ PWM11 =1 ; OBSOLETE! Use WGM11
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311 .equ PWM10 =0 ; OBSOLETE! Use WGM10
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317 .equ CTC11 =4 ; OBSOLETE! Use WGM13
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319 .equ CTC10 =3 ; OBSOLETE! Use WGM12
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321 .equ CTC1 =3 ; Old Mega161
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329 .equ PWM2 =6 ; OBSOLETE! Use WGM20
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333 .equ CTC2 =3 ; OBSOLETE! Use WGM21
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346 .equ WDCE =4 ; Added for Mega161B
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493 ;USR (for compatibility with s8515)
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506 .equ OR0 =3 ; Old name kept for compatibilty
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517 .equ OR1 =3 ; Old name kept for compatibilty
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538 ;UCR (for compatibility with s8515)
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544 .equ CHR9 =2 ; Old name kept for compatibilty
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555 .equ CHR90 =2 ; Old name kept for compatibilty
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566 .equ CHR91 =2 ; Old name kept for compatibilty
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594 .equ AINBG =6 ; Old mega161
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605 ; Boot loader Lock bit
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611 ;*****************************************************************************
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612 ; CPU Register Declarations
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613 ;*****************************************************************************
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615 .def XL = r26 ; X pointer low
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616 .def XH = r27 ; X pointer high
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617 .def YL = r28 ; Y pointer low
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618 .def YH = r29 ; Y pointer high
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619 .def ZL = r30 ; Z pointer low
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620 .def ZH = r31 ; Z pointer high
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623 ;*****************************************************************************
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624 ; Data Memory Declarations
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625 ;*****************************************************************************
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627 .equ RAMEND = $488 ; Highest internal data memory (SRAM) address.
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628 ;(1k RAM + IO + REG)
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629 .equ EEPROMEND = $01ff ; Highest EEPROM address.
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631 ;*****************************************************************************
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632 ; Program Memory Declarations
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633 ;*****************************************************************************
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635 .equ FLASHEND = $1FFF ; Highest program memory (flash) address
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636 ; (When addressed as 16 bit words)
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637 ; ( 8k words , 16k byte )
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639 ;**** Boot Vectors ****
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642 .equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B
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643 .equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B
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644 .equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB
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645 .equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB
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646 .equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility
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647 .equ PAGESIZE =64 ;number of WORDS in a page
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652 .equ INT0addr = $002 ; External Interrupt Request 0
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653 .equ INT1addr = $004 ; External Interrupt Request 1
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654 .equ INT2addr = $006 ; External Interrupt Request 2
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655 .equ PCINT0addr = $008 ; Pin Change Interrupt Request 0
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656 .equ PCINT1addr = $00A
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657 .equ TIMER3CAPTaddr = $00C
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658 .equ TIMER3COMPAaddr = $00E
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659 .equ TIMER3COMPBaddr = $010
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660 .equ TIMER3OVFaddr = $012
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661 .equ TIMER2COMPaddr = $014
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662 .equ TIMER2OVFaddr = $016
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663 .equ TIMER1CAPTaddr = $018
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664 .equ TIMER1COMPAaddr = $01A
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665 .equ TIMER1COMPBaddr = $01C
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666 .equ TIMER1OVFaddr = $01E
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667 .equ TIMER0COMPaddr = $020
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668 .equ TIMER0OVFaddr = $022
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669 .equ SPISTCaddr = $024
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670 .equ USART0RXCaddr = $026
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671 .equ USART1RXCaddr = $028
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672 .equ USART0UDREaddr = $02A
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673 .equ USART1UDREaddr = $02C
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674 .equ USART0TXCaddr = $02E
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675 .equ USART1TXCaddr = $030
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676 .equ EE_RDYaddr = $032
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677 .equ ANA_CMPaddr = $034
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678 .equ SPM_RDYaddr = $036
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