new port init + added schematic url

[my-code/atmel.git] / beginners / test_ports_uart.asm

diff --git a/beginners/test_ports_uart.asm b/beginners/test_ports_uart.asm
index f870a3e4f1878dba6e1630cf0a2bf5ded8bb53e2..bd9c3fe32a467b79727870bcf6c7180225f4151a 100644 (file)
--- a/beginners/test_ports_uart.asm
+++ b/beginners/test_ports_uart.asm
@@ -37,6 +37,12 @@ MAINLOOP:
                ldi r22,0
                INNERLOOP:
 
+                       ldi r23,0
+                       IILOOP:
+                               inc r23
+                               cpi r23,0x40
+                               brne IILOOP
+
                        inc r22
                        cpi r22,0xff
                        brne INNERLOOP