+void slave_fifo_init() {
+
+ /* initialization of the slave fifo, used by external logic (the fpga)
+ * to do usb communication with the host */
+
+ /* set bit 0 and 1 - fifo slave config */
+ IFCONFIG|=0x03;
+
+ /* async mode */
+ IFCONFIG|=0x04;
+
+ /* p. 180: must be set to 1 */
+ REVCTL|=((1<<0)|(1<<1));
+
+ /* 8 bit fifo to all endpoints
+ *
+ * ('or' of all these bits define port d functionality)
+ */
+ EP2FIFOCFG&=~(1<<0);
+ EP4FIFOCFG&=~(1<<0);
+ EP6FIFOCFG&=~(1<<0);
+ EP8FIFOCFG&=~(1<<0);
+
+ /* default indexed flag configuration:
+ *
+ * flag a: programmable level
+ * flag b: full
+ * flag c: empty
+ *
+ * todo: -> fixed configuration
+ */
+
+ /* endpoint configuration:
+ *
+ * ep2: bulk in 4x512
+ * ep6: bulk out 4x512
+ *
+ * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
+ * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
+ * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
+ */
+ EP2CFG=0xa0;
+ EP4CFG=0x01;
+ EP6CFG=0xe0;
+ EP8CFG=0x01;
+
+ /* reset the fifo */
+ FIFORESET=0x80; /* nak all transfers */
+ FIFORESET=0x02; /* reset ep2 */
+ FIFORESET=0x06; /* reset ep6 */
+ FIFORESET=0x00; /* restore normal operation */
+
+ /* auto in/out, no cpu interaction! auto in len = 512 */
+ EP2FIFOCFG|=(1<<4);
+ EP6FIFOCFG|=(1<<3);
+ EP6AUTOINLENH=(1<<1);
+ EP6AUTOINLENL=0;