+ /* endpoint configuration:
+ *
+ * (assuming 'high bandwidth in' [fpga -> host]
+ * and 'low bandwidth out' [host->fpga] applications)
+ *
+ * ep2: bulk in 3x1024
+ * ep6: bulk out 2x512
+ *
+ * 0xeb = 1 1 1 0 1 0 1 1 = bulk in 3x1024
+ * 0xa2 = 1 0 1 0 0 0 1 0 = bulk out 2x512
+ * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
+ */
+ EP2CFG=0xeb;
+ EP4CFG=0x01;
+ EP6CFG=0xa2;
+ EP8CFG=0x01;
+
+ /* reset the fifo */
+ FIFORESET=0x80; /* nak all transfers */
+ FIFORESET=0x02; /* reset ep2 */
+ FIFORESET=0x06; /* reset ep6 */
+ FIFORESET=0x00; /* restore normal operation */
+
+ /* auto in/out, no cpu interaction! auto in len = 1024 */
+ EP2FIFOCFG|=(1<<3);
+ EP2AUTOINLENH=(1<<2);
+ EP2AUTOINLENL=0;
+ EP6FIFOCFG|=(1<<4);
+
+ /* maybe OUTPKTEND necessary (with skip=1) */
+}
+
+void ep1_init() {
+
+ /* initialize endpoint 1 (will be used for jtag) */
+
+ /* endpoint 1 configuration:
+ *
+ * default (valid, bulk) fits!
+ */