reworked part of the code

diff --git a/beginners/season_junior.asm b/beginners/season_junior.asm
index 78c79627da6b99d76037ea8687a0ccb8bc8cbb0d..703b29fbe203ed2bcd020c27a2e256022968822b 100644 (file)
--- a/beginners/season_junior.asm
+++ b/beginners/season_junior.asm
@@ -33,8 +33,9 @@
 ;
 ; buffer/parse whole strings and decide whether to send to card or not.
 
-; some defines
-; ------------
+; #######
+; defines
+; #######
 
 ; baudrate = clock freq / etu
 ; std smartcard etu: 372
@@ -52,17 +53,43 @@
 .define tmp2 r19
 .define byte r20
 .define overflow_counter r21
+.define counter_l r22
+.define counter_h r23
+.define state r24
+.define state_m r25
+.define mode r26
+.define counter_l_tmp r27
+.define counter_h_tmp r28
 .define one r1
 .define zero r0
 
-
-;
+; state
+.define LOW (1<<0)
+.define LOW_F 1
+.define HIGH (1<<1)
+.define HIGH_F 2
+; mode
+.define STUPID (1<<0) ; forward cam <-> card communication
+.define STUPID_F 1
+.define COOL (1<<1) ; send time (clocks) & state via uart
+.define COOL_F 2
+.define ELITE (1<<2) ; create bytes, maybe even whole command arrays
+.define ELITE_F 3
+.define GODLIKE (1<<3) ; filter and mask for commands to card - send rejected via uart only
+.define GODLIKE_F 4
+.define INCREDIBLE_HACK (1<<4) ; destroy all your hardware
+.define INCREDIBLE_HACK_F 5 
+
+; but there is only stupid and cool mode right now %)
+
+
+; #############
 ; programm code
-; -------------
+; #############
 
-;
+; ------------------
 ; interrupt vectors:
-;
+; ------------------
 
 ; reset
 rjmp INIT
@@ -97,9 +124,9 @@ reti
 ; analog comparator
 reti
 
-;
+; ------------
 ; init routine
-;
+; ------------
 
 INIT:
 
@@ -118,7 +145,7 @@ out MCUCR,tmp
 ldi tmp,((1<<TOIE1)|(1<<TICIE1))
 out TIMSK,tmp
 ; setup t/c and icp
-ldi tmp,((1<<CS12)|(1<<CS11)|(1<<CS10)|(1<<ICNC1)|(1<<ICES1))
+ldi tmp,((1<<CS12)|(1<<CS11)|(1<<CS10)|(1<<ICNC1)|(0<<ICES1))
 out TCCR1B,tmp
 
 ; configure uart - interrupt enabled when i/o
@@ -132,6 +159,13 @@ ldi byte,0
 ldi overflow_counter,0
 ldi tmp1,0
 ldi tmp2,0 
+ldi counter_l,0
+ldi counter_h,0
+ldi state,HIGH ; .. as waiting for falling edge of start bit
+ldi state_m,0x03
+ldi mode,(STUPID|COOL)
+ldi counter_l_tmp,0
+ldi counter_h_tmp,0
 ldi tmp,1
 mov one,tmp
 ldi tmp,0
@@ -143,67 +177,76 @@ sei
 ; jump to mainloop
 rjmp MAIN
 
-;
+; ------------
 ; main routine
-;
+; ------------
 
 MAIN:
 
+; loop and wait for interrupts
 rjmp MAIN
 
-;
-; rec_card routines
-;
+; ----------------
+; rec_card routine
+; ----------------
 
 REC_CARD:
 
-; decide what to do
-sbic PORTD,PD6
-rjmp REC_CARD_HIGH
-rjmp REC_CARD_LOW
-
-REC_CARD_HIGH:
-
 ; save counter
-in r24,ICR1L
-in r25,ICR1H
+in counter_l,ICR1L
+in counter_h,ICR1H
 
-; output high on port to cam
-sbi PORTD,PD3
+; toggle state
+eor state,state_m
 
 ; toggle icp sense
-cbi TCCR1B,ICES1
-;in r16,TCCR1B
-;cbr r16,ICES1
-;out TCCR1B,r16
+rcall TOGGLE_ICP_SENSE
 
-; status tu submit
-ldi r26,1
+; fwd to cam if in stupid mode
+sbrc mode,STUPID_F
+rcall FWD_TO_CAM
 
-; enable uart dre interrupt
-sbi UCR,UDRIE
+; calculate delta clocks if in stupid mode
+sbrc mode,COOL_F
+rcall CALC_DELTA_CLOCK ; -> calc delta, store to counter_l_tmp, counter_h_tmp
 
-reti
+; send time and state via uart
+sbrc mode,COOL_F
+rcall SEND_TO_UART ; -> prepare date & enable uart dre interrupt (sbi UCR,UDRIE)
 
-REC_CARD_LOW:
+; return
+reti
 
-; save counter
-in r27,ICR1L
-in r28,ICR1H
+; ------------------------
+; toggle_icp_sense routine
+; ------------------------
 
-; output low on port to cam
-cbi PORTD,PD3
+TOGGLE_ICP_SENSE:
 
-; toggle icp sense
+; toggle according to state
+cbi TCCR1B,ICES1
+sbrs state,HIGH
 sbi TCCR1B,ICES1
 
-; status to submit
-ldi r26,0
+; return 
+ret
 
-; enable uart dre interrupt
-sbi UCR,UDRIE
+; ------------------
+; fwd_to_cam routine
+; ------------------
 
-reti
+; output state on port to cam
+mov tmp,state
+andi tmp,HIGH
+lsl tmp ; as we have to set pd3 (dirty, shorter way?)
+sbi DDRD,DDD3
+out PORTD,tmp ; <- hunz: low or high if pd3 bit is set ?
+
+; return
+ret
+
+
+; zzZZzZzZZZ .... hier gehts weiter !!!
 
 ;
 ; rec_cam routines