.def tmp2 = r17
.def uart_rxtx = r18
.def count = r19
+.def state = r20
+.def scount = r21
;
; interrupts
rjmp INIT
; INT0
-reti
+rjmp INT0_IR
; INT1
reti
reti
; T1 OVF1
-reti
+rjmp T1_OVF_IR
; T0 OVF0
-rjmp T0_OVF
+reti
; UART RX
-rjmp UART_RECEIVE
+reti
; UART UDRE
reti
; gio port init
rcall PORT_INIT
- ; timer0 init
- rcall TIMER0_INIT
-
- ; timer0 interrupt enable
- rcall TIMER0_INT_INIT
+ ; timer1 init
+ rcall TIMER1_INIT
; uart init
rcall UART_INIT
- ; uart interrupt enable
- rcall UART_INT_RX_INIT
-
; zero and one initialization
ldi tmp1,0
mov zero,tmp1
out SPL,tmp1
; more init
- ldi count,0x21
+ ldi count,0
+ ldi state,0
+
+ ; storage pointer
+ ldi ZL,low(STORAGE)
+ ldi ZH,high(STORAGE)
+
+ ldi scount,0
+ ldi tmp1,0x23
+INIT_STORAGE:
+ ; init storage
+ st Z+,tmp1
+ st Z+,tmp1
+ add scount,one
+ cpi scount,55
+ brne INIT_STORAGE
+
+ ; storage pointer again
+ ldi ZL,low(STORAGE)
+ ldi ZH,high(STORAGE)
; signal ready output
- ldi uart_rxtx,0x68
+ ldi uart_rxtx,0x72
rcall UART_TX
+DEBUG_PORT:
+ ;rcall UART_RX
+ ;ldi uart_rxtx,0x30
+ ;in tmp1,PIND
+ ;sbrc tmp1,2
+ ;ldi uart_rxtx,0x31
+ ;rcall UART_TX
+ ;rjmp DEBUG_PORT
+
+ ; external interrupt enable
+ rcall INT0_IR_CONF_INIT
+ rcall INT0_IR_ENABLE
+
; global interrupt enable
sei
MAIN:
-WAIT_FOR_HIGH:
- ; start as soon as we get a high signal
+SAMPLE:
+
+ ; sample as long as there is storage capacity and signal
+ cpi state,2
+ brne SAMPLE
+
+ ; disable interrupts
+ rcall INT0_IR_DISABLE
+ rcall TIMER1_INT_DISABLE
+
+ ; signal finish
+ ldi uart_rxtx,0x66
+ rcall UART_TX
+
+IDLE:
+
+ ; wait for commands via uart
+ rcall UART_RX
+
+ ; decode instruction
+ cpi uart_rxtx,0x52
+ breq RESET
+ cpi uart_rxtx,0x54
+ breq TRANSFER
+
+ rjmp IDLE
+
+TRANSFER:
+
+ ; reset storage pointer
+ ldi ZL,low(STORAGE)
+ ldi ZH,high(STORAGE)
+ ldi scount,1
+
+ ; transmit number of sampled words
+ mov uart_rxtx,count
+ rcall UART_TX
+
+TRANSFER_LOOP:
+
+ ; send data and counter
+ ld uart_rxtx,Z+
+ rcall UART_TX
+ ld uart_rxtx,Z+
+ rcall UART_TX
+
+ ; count sent data
+ add scount,one
- rjmp WAIT_FOR_HIGH
+ ; check amount of data
+ cpi scount,56
+ breq IDLE
+ rjmp TRANSFER_LOOP
; include subroutines
.include "port.asm"
.include "timer.asm"
.include "uart.asm"
-
;
; interrupt routines
;
-T0_OVF:
+INT0_IR:
; debug output
- cbi PORTD,3
+ ; cbi PORTD,3
- ; read port
+ ; get timer value
+ in tmp1,TCNT1L
+ in tmp2,TCNT1H
- ; store another byte into sram
+ ; check for initial or running state
+ cpi state,0
+ brne INT0_RUN
+ ; configure interrupt for running state
+ rcall INT0_IR_CONF_RUN
+ ldi state,1
- ; debug output
- sbi PORTD,3
+ ; reset timer and start ovf interrupt
+ ldi tmp1,0
+ out TCNT1H,tmp1
+ out TCNT1L,tmp1
+ rcall TIMER1_INT_ENABLE
+
+ rjmp EXIT_IR
+
+INT0_RUN:
+
+ ; write timer value into sram
+ st Z+,tmp2
+ st Z+,tmp1
+
+ ; inc counter
+ add count,one
+ ; reset timer
+ ldi tmp1,0
+ out TCNT1H,tmp1
+ out TCNT1L,tmp1
+
+ ; check for left capacity
+ cpi count,55
+ brne EXIT_IR
+
+ ; indicate end of 'c'apacity
+ ldi uart_rxtx,0x63
+ rcall UART_TX
+
+ ; exit sampling
+ ldi state,2
+
+EXIT_IR:
+
+ ; debug output
+ ; sbi PORTD,3
+
reti
-UART_RECEIVE:
+T1_OVF_IR:
+
+ ; indicate 'o'verflow end
+ ldi uart_rxtx,0x6f
+ rcall UART_TX
+
+ ; exit sampling
+ ldi state,2
+
reti
.dseg
-DATA_STORAGE: .byte 8
-
+STORAGE: .byte 110