- /*
- * idle clocks between rad & write: 0+1
- * length of read access: 1+3
- * bls lines high during write access
- * length of write access: 0+1
- * no write protect, no burst-rom
- * 16 bit data width
- */
-
- BCFG0=0x10000420; // flash 1
- BCFG2=0x10000420; // flash 2
-
- /*
- * p3.27: write enable
- * p3.25: chip select 2
- * p2.15 - p2.8: data bus
- * a[1:15] -> address lines
- */
-
- PINSEL2=(PINSEL2&P2MASK)|(1<<8);
- PINSEL2=(PINSEL2&P2MASK&~((1<<15)|(1<<14)))|(1<<14);
- PINSEL2=(PINSEL2&P2MASK&~((1<<5)|(1<<4)))|(1<<4);
- PINSEL2=(PINSEL2&P2MASK)|(1<<24);
- PINSEL2=(PINSEL2&P2MASK&~((1<<27)|(1<<26)|(1<<25)))|(1<<27)|(1<<26);