X-Git-Url: https://hackdaworld.org/gitweb/?a=blobdiff_plain;f=bibdb%2Fbibdb.bib;h=e575307a37bc3301e89a5c2ef13f34714a2bd625;hb=45c64a012b9adeee522d428c19bc6f263d7c47b9;hp=c98683febc3f028bddd741c72ea1bcaf83f3f30f;hpb=8fe6107dd7386705bd4a8b96d634cf1e8ee90659;p=lectures%2Flatex.git diff --git a/bibdb/bibdb.bib b/bibdb/bibdb.bib index c98683f..e575307 100644 --- a/bibdb/bibdb.bib +++ b/bibdb/bibdb.bib @@ -1535,15 +1535,21 @@ } @Article{zirkelbach11, - title = "Combined ab initio and classical potential simulation - study on the silicon carbide precipitation in silicon", - journal = "accepted for publication in Phys. Rev. B", - volume = "", - number = "", - pages = "", - year = "2011", + journal = "Phys. Rev. B", + month = aug, + URL = "http://link.aps.org/doi/10.1103/PhysRevB.84.064126", + publisher = "American Physical Society", author = "F. Zirkelbach and B. Stritzker and K. Nordlund and J. K. N. Lindner and W. G. Schmidt and E. Rauls", + title = "Combined \textit{ab initio} and classical potential + simulation study on silicon carbide precipitation in + silicon", + year = "2011", + pages = "064126", + numpages = "18", + volume = "84", + doi = "10.1103/PhysRevB.84.064126", + issue = "6", abstract = "Atomistic simulations on the silicon carbide precipitation in bulk silicon employing both, classical potential and first-principles methods are presented. @@ -1732,6 +1738,22 @@ notes = "c int diffusion barrier", } +@Article{haeberlen10, + title = "Structural characterization of cubic and hexagonal + Ga{N} thin films grown by {IBA}-{MBE} on Si{C}/Si", + journal = "Journal of Crystal Growth", + volume = "312", + number = "6", + pages = "762--769", + year = "2010", + note = "", + ISSN = "0022-0248", + doi = "10.1016/j.jcrysgro.2009.12.048", + URL = "http://www.sciencedirect.com/science/article/pii/S0022024809011452", + author = "M. H{\"a}berlen and J. W. Gerlach and B. Murphy and J. + K. N. Lindner and B. Stritzker", +} + @Article{ito04, title = "Ion beam synthesis of 3{C}-Si{C} layers in Si and its application in buffer layer for Ga{N} epitaxial @@ -3444,7 +3466,7 @@ } @Article{parcas_md, - title = "{PARCAS} molecular dynamics code", + journal = "{PARCAS} molecular dynamics code", author = "K. Nordlund", year = "2008", } @@ -4006,7 +4028,6 @@ title = "The Fitting of Pseudopotentials to Experimental Data and Their Subsequent Application", editor = "Frederick Seitz Henry Ehrenreich and David Turnbull", - booktitle = "", publisher = "Academic Press", year = "1970", volume = "24", @@ -5139,3 +5160,47 @@ year = "1994", publisher = "Suhrkamp", } + +% Generated at www.see-out.com/sandramau/bibpat.html on on 19/09/11 03:57:45 CDT +@Misc{ATTENBERGER:2003:misc, + author = "Wilfried ATTENBERGER and Jörg LINDNER and Bernd + STRITZKER", + title = "A {METHOD} {FOR} {FORMING} {A} {LAYERED} + {SEMICONDUCTOR} {STRUCTURE} {AND} {CORRESPONDING} + {STRUCTURE}", + year = "2003", + month = apr, + day = "24", + note = "WO 2003/034484 A3R4", + version = "A3R4", + howpublished = "Patent Application", + nationality = "WO", + URL = "http://www.patentlens.net/patentlens/patent/WO_2003_034484_A3R4/en/", + filing_num = "EP0211423", + yearfiled = "2002", + monthfiled = "10", + dayfiled = "11", + pat_refs = "", + ipc_class = "7B 81C 1/00 B; 7H 01L 21/04 B; 7H 01L 21/265 B; 7H 01L + 21/322 B; 7H 01L 21/324 B; 7H 01L 21/74 A; 7H 01L + 21/762 B; 7H 01L 29/165 B; 7H 01L 33/00 B", + us_class = "", + abstract = "The following invention provides a method for forming + a layered semiconductor structure having a layer (5) of + a first semiconductor material on a substrate (1; 1') + of at least one second semiconductor material, + comprising the steps of: providing said substrate (1; + 1'); burying said layer (5) of said first semiconductor + material in said substrate (1; 1'), said buried layer + (5) having an upper surface (105) and a lower surface + (105) and dividing said substrate (1; 1') into an upper + part (1a) and a lower part (1b; 1b', 1c); creating a + buried damage layer (10; 10'; 10'', 100'') which at + least partly adjoins and/or at least partly includes + said upper surface (105) of said buried layer (5); and + removing said upper part (1a) of said substrate (1; 1') + and said buried damage layer (10; 10'; 10'', 100'') for + exposing said buried layer (5). The invention also + provides a corresponding layered semiconductor + structure.", +}