X-Git-Url: https://hackdaworld.org/gitweb/?a=blobdiff_plain;f=monolyzer%2Fmain.asm;h=c2482c744073975c4bd2b0f714c890cd1c0ef507;hb=HEAD;hp=bcc6c1c87b1ced5d2b0adff680ac0d58cbe830fe;hpb=1117f788c441bc3d8caf90e5fb883e11696e1757;p=my-code%2Fatmel.git diff --git a/monolyzer/main.asm b/monolyzer/main.asm index bcc6c1c..c2482c7 100644 --- a/monolyzer/main.asm +++ b/monolyzer/main.asm @@ -14,6 +14,12 @@ .def uart_rxtx = r18 .def count = r19 .def state = r20 +.def scount = r21 +.def input = r22 +.def save = r23 + +;.define FLOODME +;.define S_FLOODME ; ; interrupts @@ -35,7 +41,7 @@ reti reti ; T1 OVF1 -reti +rjmp T1_OVF_IR ; T0 OVF0 reti @@ -87,7 +93,7 @@ INIT: rcall PORT_INIT ; timer1 init - rcall TIMER1_INIT + rcall TIMER1_INIT_64 ; uart init rcall UART_INIT @@ -104,23 +110,57 @@ INIT: ; more init ldi count,0 - ldi state,1 + ldi state,0 ; storage pointer ldi ZL,low(STORAGE) ldi ZH,high(STORAGE) - ; counter - ldi tmp1,0 - out TCNT1H,tmp1 - out TCNT1L,tmp1 + ldi scount,0 + ldi tmp1,0x23 +INIT_STORAGE: + ; init storage + st Z+,tmp1 + st Z+,tmp1 + add scount,one + cpi scount,55 + brne INIT_STORAGE + + ; storage pointer again + ldi ZL,low(STORAGE) + ldi ZH,high(STORAGE) ; signal ready output ldi uart_rxtx,0x72 rcall UART_TX - ; external interrupt enable - rcall INT0_IR_CONF +.ifdef FLOODME +DEBUG_PORT: + ;rcall UART_RX + ldi scount,0 +DEBUG_PORT_LOOP: + lsl uart_rxtx + in tmp1,PIND + sbrc tmp1,2 + add uart_rxtx,one + add scount,one + cpi scount,8 + brne DEBUG_PORT_LOOP + rcall UART_TX + rjmp DEBUG_PORT +.endif + +.ifdef S_FLOODME +DEBUG_PORT: + ldi uart_rxtx,0x30 + in tmp1,PIND + sbrc tmp1,2 + add uart_rxtx,one + rcall UART_TX + rjmp DEBUG_PORT +.endif + ; enable interrupts + rcall INT0_IR_CONF_R rcall INT0_IR_ENABLE ; global interrupt enable @@ -130,12 +170,9 @@ MAIN: SAMPLE: - ; sample as long as there is storage capacity - sbrc state,0 - rjmp SAMPLE - - ; external interrupt enable - rcall INT0_IR_DISABLE + ; sample as long as there is storage capacity and signal + cpi state,10 + brne SAMPLE ; signal finish ldi uart_rxtx,0x66 @@ -147,31 +184,49 @@ IDLE: rcall UART_RX ; decode instruction - cpi uart_rxtx,0x52 + cpi uart_rxtx,0x72 breq RESET - cpi uart_rxtx,0x54 + cpi uart_rxtx,0x74 breq TRANSFER + cpi uart_rxtx,0x73 + breq SINGLE_SAMPLE rjmp IDLE +SINGLE_SAMPLE: + + ; sample port d pin 2 and output via uart + ldi uart_rxtx,0x30 + in tmp2,PIND + sbrc tmp2,2 + ldi uart_rxtx,0x31 + rcall UART_TX + rjmp IDLE + TRANSFER: ; reset storage pointer ldi ZL,low(STORAGE) ldi ZH,high(STORAGE) - ldi count,0 + ldi scount,1 + + ; transmit number of sampled words + mov uart_rxtx,count + rcall UART_TX TRANSFER_LOOP: - ; transmit storage + ; send data and counter + ld uart_rxtx,Z+ + rcall UART_TX ld uart_rxtx,Z+ rcall UART_TX ; count sent data - add count,one + add scount,one - ; check amount of sent data - cpi count,110 + ; check amount of data + cpi scount,56 breq IDLE rjmp TRANSFER_LOOP @@ -187,32 +242,79 @@ TRANSFER_LOOP: INT0_IR: - ; debug output - ; cbi PORTD,3 + in save,SREG - ; write timer value into sram + cli + + ; get timer value in tmp1,TCNT1L in tmp2,TCNT1H + + ; reset timer + ldi tmp1,0 + out TCNT1H,tmp1 + out TCNT1L,tmp1 + + ; check for running state + cpi state,5 + breq INT0_RUN + + ; reconfigure int0 + rcall INT0_IR_CONF_FR + ldi state,5 + rcall TIMER1_INT_ENABLE + + rjmp LEAVE_INT0_IR + +INT0_RUN: + + ; write timer value into sram st Z+,tmp2 st Z+,tmp1 ; inc counter add count,one - + ; check for left capacity cpi count,55 - brne EXIT_IR + brne LEAVE_INT0_IR + + ; indicate end of 'c'apacity + ldi uart_rxtx,0x63 + rcall UART_TX ; exit sampling - ldi state,0 + ldi state,10 + + ; leave all interrupts cleared + rjmp EXIT_INT0_IR + +LEAVE_INT0_IR: + + sei -EXIT_IR: +EXIT_INT0_IR: - ; debug output - ; sbi PORTD,3 + out SREG,save reti +T1_OVF_IR: + + in save,SREG + + cli + + ; indicate 'o'verflow end + ldi uart_rxtx,0x6f + rcall UART_TX + + ; exit sampling + ldi state,10 + + out SREG,save + + reti ; ; sram