--- /dev/null
+;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************\r
+;***** Created: 2005-11-04 09:37 ******* Source: ATtiny2313.xml **********\r
+;*************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "tn2313def.inc"\r
+;* Title : Register/Bit Definitions for the ATtiny2313\r
+;* Date : 2005-11-04\r
+;* Version : 2.21\r
+;* Support E-mail : avr@atmel.com\r
+;* Target MCU : ATtiny2313\r
+;* \r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and \r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;* \r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"\r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;* \r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;*************************************************************************\r
+\r
+\r
+; ***** SPECIFY DEVICE ***************************************************\r
+.device ATtiny2313\r
+.equ SIGNATURE_000 = 0x1e\r
+.equ SIGNATURE_001 = 0x91\r
+.equ SIGNATURE_002 = 0x0a\r
+\r
+\r
+\r
+; ***** I/O REGISTER DEFINITIONS *****************************************\r
+; NOTE:\r
+; Definitions marked "MEMORY MAPPED"are extended I/O ports\r
+; and cannot be used with IN/OUT instructions\r
+.equ SREG = 0x3f\r
+.equ SPL = 0x3d\r
+.equ OCR0B = 0x3c\r
+.equ GIMSK = 0x3b\r
+.equ EIFR = 0x3a\r
+.equ TIMSK = 0x39\r
+.equ TIFR = 0x38\r
+.equ SPMCSR = 0x37\r
+.equ OCR0A = 0x36\r
+.equ MCUCR = 0x35\r
+.equ MCUSR = 0x34\r
+.equ TCCR0B = 0x33\r
+.equ TCNT0 = 0x32\r
+.equ OSCCAL = 0x31\r
+.equ TCCR0A = 0x30\r
+.equ TCCR1A = 0x2f\r
+.equ TCCR1B = 0x2e\r
+.equ TCNT1L = 0x2c\r
+.equ TCNT1H = 0x2d\r
+.equ OCR1AL = 0x2a\r
+.equ OCR1AH = 0x2b\r
+.equ OCR1BL = 0x28\r
+.equ OCR1BH = 0x29\r
+.equ CLKPR = 0x26\r
+.equ ICR1L = 0x24\r
+.equ ICR1H = 0x25\r
+.equ GTCCR = 0x23\r
+.equ TCCR1C = 0x22\r
+.equ WDTCR = 0x21\r
+.equ PCMSK = 0x20\r
+.equ EEAR = 0x1e\r
+.equ EEDR = 0x1d\r
+.equ EECR = 0x1c\r
+.equ PORTA = 0x1b\r
+.equ DDRA = 0x1a\r
+.equ PINA = 0x19\r
+.equ PORTB = 0x18\r
+.equ DDRB = 0x17\r
+.equ PINB = 0x16\r
+.equ GPIOR2 = 0x15\r
+.equ GPIOR1 = 0x14\r
+.equ GPIOR0 = 0x13\r
+.equ PORTD = 0x12\r
+.equ DDRD = 0x11\r
+.equ PIND = 0x10\r
+.equ USIDR = 0x0f\r
+.equ USISR = 0x0e\r
+.equ USICR = 0x0d\r
+.equ UDR = 0x0c\r
+.equ UCSRA = 0x0b\r
+.equ UCSRB = 0x0a\r
+.equ UBRRL = 0x09\r
+.equ ACSR = 0x08\r
+.equ UCSRC = 0x03\r
+.equ UBRRH = 0x02\r
+.equ DIDR = 0x01\r
+\r
+\r
+; ***** BIT DEFINITIONS **************************************************\r
+\r
+; ***** PORTB ************************\r
+; PORTB - Port B Data Register\r
+.equ PORTB0 = 0 ; Port B Data Register bit 0\r
+.equ PB0 = 0 ; For compatibility\r
+.equ PORTB1 = 1 ; Port B Data Register bit 1\r
+.equ PB1 = 1 ; For compatibility\r
+.equ PORTB2 = 2 ; Port B Data Register bit 2\r
+.equ PB2 = 2 ; For compatibility\r
+.equ PORTB3 = 3 ; Port B Data Register bit 3\r
+.equ PB3 = 3 ; For compatibility\r
+.equ PORTB4 = 4 ; Port B Data Register bit 4\r
+.equ PB4 = 4 ; For compatibility\r
+.equ PORTB5 = 5 ; Port B Data Register bit 5\r
+.equ PB5 = 5 ; For compatibility\r
+.equ PORTB6 = 6 ; Port B Data Register bit 6\r
+.equ PB6 = 6 ; For compatibility\r
+.equ PORTB7 = 7 ; Port B Data Register bit 7\r
+.equ PB7 = 7 ; For compatibility\r
+\r
+; DDRB - Port B Data Direction Register\r
+.equ DDB0 = 0 ; Port B Data Direction Register bit 0\r
+.equ DDB1 = 1 ; Port B Data Direction Register bit 1\r
+.equ DDB2 = 2 ; Port B Data Direction Register bit 2\r
+.equ DDB3 = 3 ; Port B Data Direction Register bit 3\r
+.equ DDB4 = 4 ; Port B Data Direction Register bit 4\r
+.equ DDB5 = 5 ; Port B Data Direction Register bit 5\r
+.equ DDB6 = 6 ; Port B Data Direction Register bit 6\r
+.equ DDB7 = 7 ; Port B Data Direction Register bit 7\r
+\r
+; PINB - Port B Input Pins\r
+.equ PINB0 = 0 ; Port B Input Pins bit 0\r
+.equ PINB1 = 1 ; Port B Input Pins bit 1\r
+.equ PINB2 = 2 ; Port B Input Pins bit 2\r
+.equ PINB3 = 3 ; Port B Input Pins bit 3\r
+.equ PINB4 = 4 ; Port B Input Pins bit 4\r
+.equ PINB5 = 5 ; Port B Input Pins bit 5\r
+.equ PINB6 = 6 ; Port B Input Pins bit 6\r
+.equ PINB7 = 7 ; Port B Input Pins bit 7\r
+\r
+\r
+; ***** TIMER_COUNTER_0 **************\r
+; TIMSK - Timer/Counter Interrupt Mask Register\r
+.equ OCIE0A = 0 ; Timer/Counter0 Output Compare Match A Interrupt Enable\r
+.equ TOIE0 = 1 ; Timer/Counter0 Overflow Interrupt Enable\r
+.equ OCIE0B = 2 ; Timer/Counter0 Output Compare Match B Interrupt Enable\r
+\r
+; TIFR - Timer/Counter Interrupt Flag register\r
+.equ OCF0A = 0 ; Timer/Counter0 Output Compare Flag 0A\r
+.equ TOV0 = 1 ; Timer/Counter0 Overflow Flag\r
+.equ OCF0B = 2 ; Timer/Counter0 Output Compare Flag 0B\r
+\r
+; OCR0B - Timer/Counter0 Output Compare Register\r
+.equ OCR0_0 = 0 ; \r
+.equ OCR0_1 = 1 ; \r
+.equ OCR0_2 = 2 ; \r
+.equ OCR0_3 = 3 ; \r
+.equ OCR0_4 = 4 ; \r
+.equ OCR0_5 = 5 ; \r
+.equ OCR0_6 = 6 ; \r
+.equ OCR0_7 = 7 ; \r
+\r
+; OCR0A - Timer/Counter0 Output Compare Register\r
+;.equ OCR0_0 = 0 ; \r
+;.equ OCR0_1 = 1 ; \r
+;.equ OCR0_2 = 2 ; \r
+;.equ OCR0_3 = 3 ; \r
+;.equ OCR0_4 = 4 ; \r
+;.equ OCR0_5 = 5 ; \r
+;.equ OCR0_6 = 6 ; \r
+;.equ OCR0_7 = 7 ; \r
+\r
+; TCCR0A - Timer/Counter Control Register A\r
+.equ WGM00 = 0 ; Waveform Generation Mode\r
+.equ WGM01 = 1 ; Waveform Generation Mode\r
+.equ COM0B0 = 4 ; Compare Match Output B Mode\r
+.equ COM0B1 = 5 ; Compare Match Output B Mode\r
+.equ COM0A0 = 6 ; Compare Match Output A Mode\r
+.equ COM0A1 = 7 ; Compare Match Output A Mode\r
+\r
+; TCNT0 - Timer/Counter0\r
+.equ TCNT0_0 = 0 ; \r
+.equ TCNT0_1 = 1 ; \r
+.equ TCNT0_2 = 2 ; \r
+.equ TCNT0_3 = 3 ; \r
+.equ TCNT0_4 = 4 ; \r
+.equ TCNT0_5 = 5 ; \r
+.equ TCNT0_6 = 6 ; \r
+.equ TCNT0_7 = 7 ; \r
+\r
+; TCCR0B - Timer/Counter Control Register B\r
+.equ TCCR0 = TCCR0B ; For compatibility\r
+.equ CS00 = 0 ; Clock Select\r
+.equ CS01 = 1 ; Clock Select\r
+.equ CS02 = 2 ; Clock Select\r
+.equ WGM02 = 3 ; \r
+.equ FOC0B = 6 ; Force Output Compare B\r
+.equ FOC0A = 7 ; Force Output Compare B\r
+\r
+\r
+; ***** TIMER_COUNTER_1 **************\r
+; TIMSK - Timer/Counter Interrupt Mask Register\r
+.equ ICIE1 = 3 ; Timer/Counter1 Input Capture Interrupt Enable\r
+.equ TICIE = ICIE1 ; For compatibility\r
+.equ OCIE1B = 5 ; Timer/Counter1 Output CompareB Match Interrupt Enable\r
+.equ OCIE1A = 6 ; Timer/Counter1 Output CompareA Match Interrupt Enable\r
+.equ TOIE1 = 7 ; Timer/Counter1 Overflow Interrupt Enable\r
+\r
+; TIFR - Timer/Counter Interrupt Flag register\r
+.equ ICF1 = 3 ; Input Capture Flag 1\r
+.equ OCF1B = 5 ; Output Compare Flag 1B\r
+.equ OCF1A = 6 ; Output Compare Flag 1A\r
+.equ TOV1 = 7 ; Timer/Counter1 Overflow Flag\r
+\r
+; TCCR1A - Timer/Counter1 Control Register A\r
+.equ WGM10 = 0 ; Pulse Width Modulator Select Bit 0\r
+.equ PWM10 = WGM10 ; For compatibility\r
+.equ WGM11 = 1 ; Pulse Width Modulator Select Bit 1\r
+.equ PWM11 = WGM11 ; For compatibility\r
+.equ COM1B0 = 4 ; Comparet Ouput Mode 1B, bit 0\r
+.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1\r
+.equ COM1A0 = 6 ; Comparet Ouput Mode 1A, bit 0\r
+.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1\r
+\r
+; TCCR1B - Timer/Counter1 Control Register B\r
+.equ CS10 = 0 ; Clock Select bit 0\r
+.equ CS11 = 1 ; Clock Select 1 bit 1\r
+.equ CS12 = 2 ; Clock Select1 bit 2\r
+.equ WGM12 = 3 ; Waveform Generation Mode Bit 2\r
+.equ CTC1 = WGM12 ; For compatibility\r
+.equ WGM13 = 4 ; Waveform Generation Mode Bit 3\r
+.equ ICES1 = 6 ; Input Capture 1 Edge Select\r
+.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler\r
+\r
+; TCCR1C - Timer/Counter1 Control Register C\r
+.equ FOC1B = 6 ; Force Output Compare for Channel B\r
+.equ FOC1A = 7 ; Force Output Compare for Channel A\r
+\r
+\r
+; ***** WATCHDOG *********************\r
+; WDTCR - Watchdog Timer Control Register\r
+.equ WDTCSR = WDTCR ; For compatibility\r
+.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0\r
+.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1\r
+.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2\r
+.equ WDE = 3 ; Watch Dog Enable\r
+.equ WDCE = 4 ; Watchdog Change Enable\r
+.equ WDTOE = WDCE ; For compatibility\r
+.equ WDP3 = 5 ; Watchdog Timer Prescaler Bit 3\r
+.equ WDIE = 6 ; Watchdog Timeout Interrupt Enable\r
+.equ WDIF = 7 ; Watchdog Timeout Interrupt Flag\r
+\r
+\r
+; ***** EXTERNAL_INTERRUPT ***********\r
+; GIMSK - General Interrupt Mask Register\r
+.equ PCIE = 5 ; \r
+.equ INT0 = 6 ; External Interrupt Request 0 Enable\r
+.equ INT1 = 7 ; External Interrupt Request 1 Enable\r
+\r
+; EIFR - Extended Interrupt Flag Register\r
+.equ GIFR = EIFR ; For compatibility\r
+.equ PCIF = 5 ; \r
+.equ INTF0 = 6 ; External Interrupt Flag 0\r
+.equ INTF1 = 7 ; External Interrupt Flag 1\r
+\r
+\r
+; ***** USART ************************\r
+; UDR - USART I/O Data Register\r
+.equ UDR0 = 0 ; USART I/O Data Register bit 0\r
+.equ UDR1 = 1 ; USART I/O Data Register bit 1\r
+.equ UDR2 = 2 ; USART I/O Data Register bit 2\r
+.equ UDR3 = 3 ; USART I/O Data Register bit 3\r
+.equ UDR4 = 4 ; USART I/O Data Register bit 4\r
+.equ UDR5 = 5 ; USART I/O Data Register bit 5\r
+.equ UDR6 = 6 ; USART I/O Data Register bit 6\r
+.equ UDR7 = 7 ; USART I/O Data Register bit 7\r
+\r
+; UCSRA - USART Control and Status Register A\r
+.equ USR = UCSRA ; For compatibility\r
+.equ MPCM = 0 ; Multi-processor Communication Mode\r
+.equ U2X = 1 ; Double the USART Transmission Speed\r
+.equ UPE = 2 ; USART Parity Error\r
+.equ PE = UPE ; For compatibility\r
+.equ DOR = 3 ; Data overRun\r
+.equ FE = 4 ; Framing Error\r
+.equ UDRE = 5 ; USART Data Register Empty\r
+.equ TXC = 6 ; USART Transmitt Complete\r
+.equ RXC = 7 ; USART Receive Complete\r
+\r
+; UCSRB - USART Control and Status Register B\r
+.equ UCR = UCSRB ; For compatibility\r
+.equ TXB8 = 0 ; Transmit Data Bit 8\r
+.equ RXB8 = 1 ; Receive Data Bit 8\r
+.equ UCSZ2 = 2 ; Character Size\r
+.equ CHR9 = UCSZ2 ; For compatibility\r
+.equ TXEN = 3 ; Transmitter Enable\r
+.equ RXEN = 4 ; Receiver Enable\r
+.equ UDRIE = 5 ; USART Data register Empty Interrupt Enable\r
+.equ TXCIE = 6 ; TX Complete Interrupt Enable\r
+.equ RXCIE = 7 ; RX Complete Interrupt Enable\r
+\r
+; UCSRC - USART Control and Status Register C\r
+.equ UCPOL = 0 ; Clock Polarity\r
+.equ UCSZ0 = 1 ; Character Size Bit 0\r
+.equ UCSZ1 = 2 ; Character Size Bit 1\r
+.equ USBS = 3 ; Stop Bit Select\r
+.equ UPM0 = 4 ; Parity Mode Bit 0\r
+.equ UPM1 = 5 ; Parity Mode Bit 1\r
+.equ UMSEL = 6 ; USART Mode Select\r
+\r
+.equ UBRR = UBRRL ; For compatibility\r
+\r
+; ***** ANALOG_COMPARATOR ************\r
+; ACSR - Analog Comparator Control And Status Register\r
+.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0\r
+.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1\r
+.equ ACIC = 2 ; \r
+.equ ACIE = 3 ; Analog Comparator Interrupt Enable\r
+.equ ACI = 4 ; Analog Comparator Interrupt Flag\r
+.equ ACO = 5 ; Analog Compare Output\r
+.equ ACBG = 6 ; Analog Comparator Bandgap Select\r
+.equ ACD = 7 ; Analog Comparator Disable\r
+\r
+; DIDR - Digital Input Disable Register 1\r
+.equ AIN0D = 0 ; AIN0 Digital Input Disable\r
+.equ AIN1D = 1 ; AIN1 Digital Input Disable\r
+\r
+\r
+; ***** PORTD ************************\r
+; PORTD - Data Register, Port D\r
+.equ PORTD0 = 0 ; \r
+.equ PD0 = 0 ; For compatibility\r
+.equ PORTD1 = 1 ; \r
+.equ PD1 = 1 ; For compatibility\r
+.equ PORTD2 = 2 ; \r
+.equ PD2 = 2 ; For compatibility\r
+.equ PORTD3 = 3 ; \r
+.equ PD3 = 3 ; For compatibility\r
+.equ PORTD4 = 4 ; \r
+.equ PD4 = 4 ; For compatibility\r
+.equ PORTD5 = 5 ; \r
+.equ PD5 = 5 ; For compatibility\r
+.equ PORTD6 = 6 ; \r
+.equ PD6 = 6 ; For compatibility\r
+\r
+; DDRD\r
+.equ DDD0 = 0 ; \r
+.equ DDD1 = 1 ; \r
+.equ DDD2 = 2 ; \r
+.equ DDD3 = 3 ; \r
+.equ DDD4 = 4 ; \r
+.equ DDD5 = 5 ; \r
+.equ DDD6 = 6 ; \r
+\r
+; PIND - Input Pins, Port D\r
+.equ PIND0 = 0 ; \r
+.equ PIND1 = 1 ; \r
+.equ PIND2 = 2 ; \r
+.equ PIND3 = 3 ; \r
+.equ PIND4 = 4 ; \r
+.equ PIND5 = 5 ; \r
+.equ PIND6 = 6 ; \r
+\r
+\r
+; ***** EEPROM ***********************\r
+; EEAR - EEPROM Read/Write Access\r
+.equ EEARL = EEAR ; For compatibility\r
+.equ EEAR0 = 0 ; EEPROM Read/Write Access bit 0\r
+.equ EEAR1 = 1 ; EEPROM Read/Write Access bit 1\r
+.equ EEAR2 = 2 ; EEPROM Read/Write Access bit 2\r
+.equ EEAR3 = 3 ; EEPROM Read/Write Access bit 3\r
+.equ EEAR4 = 4 ; EEPROM Read/Write Access bit 4\r
+.equ EEAR5 = 5 ; EEPROM Read/Write Access bit 5\r
+.equ EEAR6 = 6 ; EEPROM Read/Write Access bit 6\r
+\r
+; EEDR - EEPROM Data Register\r
+.equ EEDR0 = 0 ; EEPROM Data Register bit 0\r
+.equ EEDR1 = 1 ; EEPROM Data Register bit 1\r
+.equ EEDR2 = 2 ; EEPROM Data Register bit 2\r
+.equ EEDR3 = 3 ; EEPROM Data Register bit 3\r
+.equ EEDR4 = 4 ; EEPROM Data Register bit 4\r
+.equ EEDR5 = 5 ; EEPROM Data Register bit 5\r
+.equ EEDR6 = 6 ; EEPROM Data Register bit 6\r
+.equ EEDR7 = 7 ; EEPROM Data Register bit 7\r
+\r
+; EECR - EEPROM Control Register\r
+.equ EERE = 0 ; EEPROM Read Enable\r
+.equ EEPE = 1 ; EEPROM Write Enable\r
+.equ EEWE = EEPE ; For compatibility\r
+.equ EEMPE = 2 ; EEPROM Master Write Enable\r
+.equ EEMWE = EEMPE ; For compatibility\r
+.equ EERIE = 3 ; EEProm Ready Interrupt Enable\r
+.equ EEPM0 = 4 ; \r
+.equ EEPM1 = 5 ; \r
+\r
+\r
+; ***** PORTA ************************\r
+; PORTA - Port A Data Register\r
+.equ PORTA0 = 0 ; Port A Data Register bit 0\r
+.equ PA0 = 0 ; For compatibility\r
+.equ PORTA1 = 1 ; Port A Data Register bit 1\r
+.equ PA1 = 1 ; For compatibility\r
+.equ PORTA2 = 2 ; Port A Data Register bit 2\r
+.equ PA2 = 2 ; For compatibility\r
+\r
+; DDRA - Port A Data Direction Register\r
+.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0\r
+.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1\r
+.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2\r
+\r
+; PINA - Port A Input Pins\r
+.equ PINA0 = 0 ; Input Pins, Port A bit 0\r
+.equ PINA1 = 1 ; Input Pins, Port A bit 1\r
+.equ PINA2 = 2 ; Input Pins, Port A bit 2\r
+\r
+\r
+; ***** CPU **************************\r
+; SREG - Status Register\r
+.equ SREG_C = 0 ; Carry Flag\r
+.equ SREG_Z = 1 ; Zero Flag\r
+.equ SREG_N = 2 ; Negative Flag\r
+.equ SREG_V = 3 ; Two's Complement Overflow Flag\r
+.equ SREG_S = 4 ; Sign Bit\r
+.equ SREG_H = 5 ; Half Carry Flag\r
+.equ SREG_T = 6 ; Bit Copy Storage\r
+.equ SREG_I = 7 ; Global Interrupt Enable\r
+\r
+; SPMCSR - Store Program Memory Control and Status register\r
+.equ SPMEN = 0 ; Store Program Memory Enable\r
+.equ PGERS = 1 ; Page Erase\r
+.equ PGWRT = 2 ; Page Write\r
+.equ RFLB = 3 ; Read Fuse and Lock Bits\r
+.equ CTPB = 4\r
+\r
+; MCUCR - MCU Control Register\r
+.equ ISC00 = 0 ; Interrupt Sense Control 0 bit 0\r
+.equ ISC01 = 1 ; Interrupt Sense Control 0 bit 1\r
+.equ ISC10 = 2 ; Interrupt Sense Control 1 bit 0\r
+.equ ISC11 = 3 ; Interrupt Sense Control 1 bit 1\r
+.equ SM0 = 4 ; Sleep Mode Select Bit 0\r
+.equ SM = SM0 ; For compatibility\r
+.equ SE = 5 ; Sleep Enable\r
+.equ SM1 = 6 ; Sleep Mode Select Bit 1\r
+.equ PUD = 7 ; Pull-up Disable\r
+\r
+; CLKPR - Clock Prescale Register\r
+.equ CLKPS0 = 0 ; Clock Prescaler Select Bit 0\r
+.equ CLKPS1 = 1 ; Clock Prescaler Select Bit 1\r
+.equ CLKPS2 = 2 ; Clock Prescaler Select Bit 2\r
+.equ CLKPS3 = 3 ; Clock Prescaler Select Bit 3\r
+.equ CLKPCE = 7 ; Clock Prescaler Change Enable\r
+\r
+; MCUSR - MCU Status register\r
+.equ PORF = 0 ; Power-On Reset Flag\r
+.equ EXTRF = 1 ; External Reset Flag\r
+.equ BORF = 2 ; Brown-out Reset Flag\r
+.equ WDRF = 3 ; Watchdog Reset Flag\r
+\r
+; OSCCAL - Oscillator Calibration Register\r
+.equ CAL0 = 0 ; Oscillatro Calibration Value Bit 0\r
+.equ CAL1 = 1 ; Oscillatro Calibration Value Bit 1\r
+.equ CAL2 = 2 ; Oscillatro Calibration Value Bit 2\r
+.equ CAL3 = 3 ; Oscillatro Calibration Value Bit 3\r
+.equ CAL4 = 4 ; Oscillatro Calibration Value Bit 4\r
+.equ CAL5 = 5 ; Oscillatro Calibration Value Bit 5\r
+.equ CAL6 = 6 ; Oscillatro Calibration Value Bit 6\r
+\r
+; GTCCR - General Timer Counter Control Register\r
+.equ SFIOR = GTCCR ; For compatibility\r
+.equ PSR10 = 0 ; \r
+\r
+; PCMSK - Pin-Change Mask register\r
+.equ PCINT0 = 0 ; Pin-Change Interrupt 0\r
+.equ PCINT1 = 1 ; Pin-Change Interrupt 1\r
+.equ PCINT2 = 2 ; Pin-Change Interrupt 2\r
+.equ PCINT3 = 3 ; Pin-Change Interrupt 3\r
+.equ PCINT4 = 4 ; Pin-Change Interrupt 4\r
+.equ PCINT5 = 5 ; Pin-Change Interrupt 5\r
+.equ PCINT6 = 6 ; Pin-Change Interrupt 6\r
+.equ PCINT7 = 7 ; Pin-Change Interrupt 7\r
+\r
+; GPIOR2 - General Purpose I/O Register 2\r
+.equ GPIOR20 = 0 ; General Purpose I/O Register 2 bit 0\r
+.equ GPIOR21 = 1 ; General Purpose I/O Register 2 bit 1\r
+.equ GPIOR22 = 2 ; General Purpose I/O Register 2 bit 2\r
+.equ GPIOR23 = 3 ; General Purpose I/O Register 2 bit 3\r
+.equ GPIOR24 = 4 ; General Purpose I/O Register 2 bit 4\r
+.equ GPIOR25 = 5 ; General Purpose I/O Register 2 bit 5\r
+.equ GPIOR26 = 6 ; General Purpose I/O Register 2 bit 6\r
+.equ GPIOR27 = 7 ; General Purpose I/O Register 2 bit 7\r
+\r
+; GPIOR1 - General Purpose I/O Register 1\r
+.equ GPIOR10 = 0 ; General Purpose I/O Register 1 bit 0\r
+.equ GPIOR11 = 1 ; General Purpose I/O Register 1 bit 1\r
+.equ GPIOR12 = 2 ; General Purpose I/O Register 1 bit 2\r
+.equ GPIOR13 = 3 ; General Purpose I/O Register 1 bit 3\r
+.equ GPIOR14 = 4 ; General Purpose I/O Register 1 bit 4\r
+.equ GPIOR15 = 5 ; General Purpose I/O Register 1 bit 5\r
+.equ GPIOR16 = 6 ; General Purpose I/O Register 1 bit 6\r
+.equ GPIOR17 = 7 ; General Purpose I/O Register 1 bit 7\r
+\r
+; GPIOR0 - General Purpose I/O Register 0\r
+.equ GPIOR00 = 0 ; General Purpose I/O Register 0 bit 0\r
+.equ GPIOR01 = 1 ; General Purpose I/O Register 0 bit 1\r
+.equ GPIOR02 = 2 ; General Purpose I/O Register 0 bit 2\r
+.equ GPIOR03 = 3 ; General Purpose I/O Register 0 bit 3\r
+.equ GPIOR04 = 4 ; General Purpose I/O Register 0 bit 4\r
+.equ GPIOR05 = 5 ; General Purpose I/O Register 0 bit 5\r
+.equ GPIOR06 = 6 ; General Purpose I/O Register 0 bit 6\r
+.equ GPIOR07 = 7 ; General Purpose I/O Register 0 bit 7\r
+\r
+\r
+; ***** USI **************************\r
+; USIDR - USI Data Register\r
+.equ USIDR0 = 0 ; USI Data Register bit 0\r
+.equ USIDR1 = 1 ; USI Data Register bit 1\r
+.equ USIDR2 = 2 ; USI Data Register bit 2\r
+.equ USIDR3 = 3 ; USI Data Register bit 3\r
+.equ USIDR4 = 4 ; USI Data Register bit 4\r
+.equ USIDR5 = 5 ; USI Data Register bit 5\r
+.equ USIDR6 = 6 ; USI Data Register bit 6\r
+.equ USIDR7 = 7 ; USI Data Register bit 7\r
+\r
+; USISR - USI Status Register\r
+.equ USICNT0 = 0 ; USI Counter Value Bit 0\r
+.equ USICNT1 = 1 ; USI Counter Value Bit 1\r
+.equ USICNT2 = 2 ; USI Counter Value Bit 2\r
+.equ USICNT3 = 3 ; USI Counter Value Bit 3\r
+.equ USIDC = 4 ; Data Output Collision\r
+.equ USIPF = 5 ; Stop Condition Flag\r
+.equ USIOIF = 6 ; Counter Overflow Interrupt Flag\r
+.equ USISIF = 7 ; Start Condition Interrupt Flag\r
+\r
+; USICR - USI Control Register\r
+.equ USITC = 0 ; Toggle Clock Port Pin\r
+.equ USICLK = 1 ; Clock Strobe\r
+.equ USICS0 = 2 ; USI Clock Source Select Bit 0\r
+.equ USICS1 = 3 ; USI Clock Source Select Bit 1\r
+.equ USIWM0 = 4 ; USI Wire Mode Bit 0\r
+.equ USIWM1 = 5 ; USI Wire Mode Bit 1\r
+.equ USIOIE = 6 ; Counter Overflow Interrupt Enable\r
+.equ USISIE = 7 ; Start Condition Interrupt Enable\r
+\r
+\r
+\r
+; ***** LOCKSBITS ********************************************************\r
+.equ LB1 = 0 ; Lockbit\r
+.equ LB2 = 1 ; Lockbit\r
+\r
+\r
+; ***** FUSES ************************************************************\r
+; LOW fuse bits\r
+.equ CKSEL0 = 0 ; Select Clock Source\r
+.equ CKSEL1 = 1 ; Select Clock Source\r
+.equ CKSEL2 = 2 ; Select Clock Source\r
+.equ CKSEL3 = 3 ; Select Clock Source\r
+.equ SUT0 = 4 ; Select start-up time\r
+.equ SUT1 = 5 ; Select start-up time\r
+.equ CKOUT = 6 ; Clock output\r
+.equ CKDIV8 = 7 ; Divide clock by 8\r
+\r
+; HIGH fuse bits\r
+.equ BODLEVEL0 = 0 ; Brown-out Detector trigger level\r
+.equ BODLEVEL1 = 1 ; Brown-out Detector trigger level\r
+.equ BODLEVEL2 = 2 ; Brown-out Detector trigger level\r
+.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase\r
+.equ WDTON = 4 ; Watchdog Timer Always On\r
+.equ SPIEN = 5 ; Enable Serial programming and Data Downloading\r
+.equ DWEN = 6 ; debugWIRE Enable\r
+.equ RSTDISBL = 7 ; External reset disable\r
+\r
+; EXTENDED fuse bits\r
+.equ SELFPRGEN = 0 ; Self Programming Enable\r
+\r
+\r
+\r
+; ***** CPU REGISTER DEFINITIONS *****************************************\r
+.def XH = r27\r
+.def XL = r26\r
+.def YH = r29\r
+.def YL = r28\r
+.def ZH = r31\r
+.def ZL = r30\r
+\r
+\r
+\r
+; ***** DATA MEMORY DECLARATIONS *****************************************\r
+.equ FLASHEND = 0x03ff ; Note: Word address\r
+.equ IOEND = 0x003f\r
+.equ SRAM_START = 0x0060\r
+.equ SRAM_SIZE = 128\r
+.equ RAMEND = 0x00df\r
+.equ XRAMEND = 0x0000\r
+.equ E2END = 0x007f\r
+.equ EEPROMEND = 0x007f\r
+.equ EEADRBITS = 7\r
+\r
+\r
+\r
+; ***** BOOTLOADER DECLARATIONS ******************************************\r
+.equ NRWW_START_ADDR = 0x0\r
+.equ NRWW_STOP_ADDR = 0x3ff\r
+.equ RWW_START_ADDR = 0x0\r
+.equ RWW_STOP_ADDR = 0x0\r
+.equ PAGESIZE = 16\r
+\r
+\r
+\r
+; ***** INTERRUPT VECTORS ************************************************\r
+.equ INT0addr = 0x0001 ; External Interrupt Request 0\r
+.equ INT1addr = 0x0002 ; External Interrupt Request 1\r
+.equ ICP1addr = 0x0003 ; Timer/Counter1 Capture Event\r
+.equ OC1Aaddr = 0x0004 ; Timer/Counter1 Compare Match A\r
+.equ OC1addr = 0x0004 ; For compatibility\r
+.equ OVF1addr = 0x0005 ; Timer/Counter1 Overflow\r
+.equ OVF0addr = 0x0006 ; Timer/Counter0 Overflow\r
+.equ URXCaddr = 0x0007 ; USART, Rx Complete\r
+.equ URXC0addr = 0x0007 ; For compatibility\r
+.equ UDREaddr = 0x0008 ; USART Data Register Empty\r
+.equ UDRE0addr = 0x0008 ; For compatibility\r
+.equ UTXCaddr = 0x0009 ; USART, Tx Complete\r
+.equ UTXC0addr = 0x0009 ; For compatibility\r
+.equ ACIaddr = 0x000a ; Analog Comparator\r
+.equ PCIaddr = 0x000b ; \r
+.equ OC1Baddr = 0x000c ; \r
+.equ OC0Aaddr = 0x000d ; \r
+.equ OC0Baddr = 0x000e ; \r
+.equ USI_STARTaddr = 0x000f ; USI Start Condition\r
+.equ USI_OVFaddr = 0x0010 ; USI Overflow\r
+.equ ERDYaddr = 0x0011 ; \r
+.equ WDTaddr = 0x0012 ; Watchdog Timer Overflow\r
+\r
+.equ INT_VECTORS_SIZE = 19 ; size in words\r
+\r
+\r
+; ***** END OF FILE ******************************************************\r
projects / my-code / atmel.git / commitdiff