.equ fiq_disable, 0x40
.equ irq_disable, 0x80
+.equ vic_vect_addr, 0xfffff030
+
#
# the startup code
#
# - that's the vectored address register
# - the vic put in there the address of our service routine
+exception_vectors:
+
ldr pc, handler_reset
ldr pc, handler_undef_instruction
ldr pc, handler_soft_ir
ldr pc, handler_data_abort
nop
ldr pc, [pc, #-0xff0]
+ #ldr pc, handler_irq
ldr pc, handler_fiq
handler_reset: .word handle_reset
handler_soft_ir: .word interrupt_handler_soft_ir
handler_prefetch_abort: .word interrupt_handler_prefetch_abort
handler_data_abort: .word interrupt_handler_data_abort
+handler_irq: .word vic_vect_addr
handler_fiq: .word interrupt_handler_fiq
# reset handling goes here
ldr r0, =stack_limit
mov sl, r0
+ # enable irq and fiq
+ msr cpsr_c, #mode_system
+
# copy data section (only if we are in flash <=> _etext != _data)
ldr r1, =_etext
ldr r3, =_edata
cmp r1, r2
- beq start_of_c_code
+ beq copy_exception_vectors
copy_data_loop:
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo copy_data_loop
+ b start_of_c_code
+
+ # copy exception vectors (only if we are in ram <=> _etext = _data)
+
+copy_exception_vectors:
+
+ mov r0, #sram_addr
+ ldr r1, =exception_vectors
+ ldmia r1!, {r2-r9}
+ stmia r0!, {r2-r9}
+ ldmia r1!, {r2-r8}
+ stmia r0!, {r2-r8}
# jump to c code