arrrrgh!

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index 8795636ee213fef05e12abd34d1b8fd716b77290..c2482c744073975c4bd2b0f714c890cd1c0ef507 100644 (file)
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -15,6 +15,11 @@
 .def   count           = r19
 .def   state           = r20
 .def   scount          = r21
+.def   input           = r22
+.def   save            = r23
+
+;.define FLOODME
+;.define S_FLOODME
 
 ;
 ; interrupts
@@ -88,7 +93,7 @@ INIT:
        rcall PORT_INIT
 
        ; timer1 init
-       rcall TIMER1_INIT
+       rcall TIMER1_INIT_64
 
        ; uart init
        rcall UART_INIT
@@ -129,17 +134,33 @@ INIT_STORAGE:
        ldi uart_rxtx,0x72
        rcall UART_TX
 
+.ifdef FLOODME
 DEBUG_PORT:
        ;rcall UART_RX
-       ;ldi uart_rxtx,0x30
-       ;in tmp1,PIND
-       ;sbrc tmp1,2
-       ;ldi uart_rxtx,0x31
-       ;rcall UART_TX
-       ;rjmp DEBUG_PORT
-
-       ; external interrupt enable
-       rcall INT0_IR_CONF_INIT
+       ldi scount,0
+DEBUG_PORT_LOOP:
+       lsl uart_rxtx
+       in tmp1,PIND
+       sbrc tmp1,2
+       add uart_rxtx,one
+       add scount,one
+       cpi scount,8
+       brne DEBUG_PORT_LOOP
+       rcall UART_TX
+       rjmp DEBUG_PORT
+.endif
+
+.ifdef S_FLOODME
+DEBUG_PORT:
+       ldi uart_rxtx,0x30
+       in tmp1,PIND
+       sbrc tmp1,2
+       add uart_rxtx,one
+       rcall UART_TX
+       rjmp DEBUG_PORT
+.endif
+       ; enable interrupts
+       rcall INT0_IR_CONF_R
        rcall INT0_IR_ENABLE
 
        ; global interrupt enable
@@ -150,13 +171,9 @@ MAIN:
 SAMPLE:
 
        ; sample as long as there is storage capacity and signal
-       cpi state,2
+       cpi state,10
        brne SAMPLE
 
-       ; disable interrupts
-       rcall INT0_IR_DISABLE
-       rcall TIMER1_INT_DISABLE
-
        ; signal finish
        ldi uart_rxtx,0x66
        rcall UART_TX
@@ -167,13 +184,25 @@ IDLE:
        rcall UART_RX
 
        ; decode instruction
-       cpi uart_rxtx,0x52
+       cpi uart_rxtx,0x72
        breq RESET
-       cpi uart_rxtx,0x54
+       cpi uart_rxtx,0x74
        breq TRANSFER
+       cpi uart_rxtx,0x73
+       breq SINGLE_SAMPLE
 
        rjmp IDLE
 
+SINGLE_SAMPLE:
+
+       ; sample port d pin 2 and output via uart
+       ldi uart_rxtx,0x30
+       in tmp2,PIND
+       sbrc tmp2,2
+       ldi uart_rxtx,0x31
+       rcall UART_TX
+       rjmp IDLE
+
 TRANSFER:
 
        ; reset storage pointer
@@ -213,28 +242,29 @@ TRANSFER_LOOP:
 
 INT0_IR:
 
-       ; debug output
-       ; cbi PORTD,3
+       in save,SREG
+
+       cli
 
        ; get timer value
        in tmp1,TCNT1L
        in tmp2,TCNT1H
 
-       ; check for initial or running state
-       cpi state,0
-       brne INT0_RUN
-
-       ; configure interrupt for running state
-       rcall INT0_IR_CONF_RUN
-       ldi state,1
-
-       ; reset timer and start ovf interrupt
+       ; reset timer
        ldi tmp1,0
        out TCNT1H,tmp1
        out TCNT1L,tmp1
+
+       ; check for running state
+       cpi state,5
+       breq INT0_RUN
+
+       ; reconfigure int0
+       rcall INT0_IR_CONF_FR
+       ldi state,5
        rcall TIMER1_INT_ENABLE
 
-       rjmp EXIT_IR
+       rjmp LEAVE_INT0_IR
 
 INT0_RUN:
 
@@ -245,40 +275,46 @@ INT0_RUN:
        ; inc counter
        add count,one
        
-       ; reset timer
-       ldi tmp1,0
-       out TCNT1H,tmp1
-       out TCNT1L,tmp1
-
        ; check for left capacity
        cpi count,55
-       brne EXIT_IR
+       brne LEAVE_INT0_IR
 
        ; indicate end of 'c'apacity
        ldi uart_rxtx,0x63
        rcall UART_TX
 
        ; exit sampling
-       ldi state,2
+       ldi state,10
 
-EXIT_IR:
+       ; leave all interrupts cleared
+       rjmp EXIT_INT0_IR
 
-       ; debug output
-       ; sbi PORTD,3
+LEAVE_INT0_IR:
+
+       sei
+
+EXIT_INT0_IR:
+
+       out SREG,save
 
        reti
 
 T1_OVF_IR:
 
+       in save,SREG
+
+       cli
+
        ; indicate 'o'verflow end
        ldi uart_rxtx,0x6f
        rcall UART_TX
 
        ; exit sampling
-       ldi state,2
+       ldi state,10
 
-       reti
+       out SREG,save
 
+       reti
 
 ;
 ; sram

diff --git a/monolyzer/port.asm b/monolyzer/port.asm
index 42c08fa912e3d2c09f6a52259d145465fffd96a0..85c57e1d63963a504e436ba5828de2bca52bc2d5 100644 (file)
--- a/monolyzer/port.asm
+++ b/monolyzer/port.asm
@@ -6,7 +6,7 @@ PORT_INIT:
        cbi DDRD,2
 
        ; switch pull-up off (useless, default)
-       cbi DDRD,2
+       cbi PORTD,2
 
        ; port d pin 6 -> output
        sbi DDRD,6
@@ -19,8 +19,7 @@ PORT_INIT:
 
        ret
 
-
-INT0_IR_CONF_INIT:
+INT0_IR_CONF_R:
 
        ; trigger interrupt on rising edge
        in tmp1,MCUCR
@@ -30,7 +29,17 @@ INT0_IR_CONF_INIT:
 
        ret
 
-INT0_IR_CONF_RUN:
+INT0_IR_CONF_F:
+
+       ; trigger interrupt on rising edge
+       in tmp1,MCUCR
+       sbr tmp1,(1<<ISC01)
+       cbr tmp1,(1<<ISC00)
+       out MCUCR,tmp1
+
+       ret
+
+INT0_IR_CONF_FR:
 
        ; trigger interrupt on falling and rising edge
        in tmp1,MCUCR

diff --git a/monolyzer/timer.asm b/monolyzer/timer.asm
index 91cfba80d6a885ec92b39120208d92aff22eb111..f5297fe0ca4c3fe8200c3c521e30a11c286f7cf7 100644 (file)
--- a/monolyzer/timer.asm
+++ b/monolyzer/timer.asm
@@ -1,6 +1,28 @@
 ; timer functions
 
-TIMER1_INIT:
+TIMER1_INIT_NP:
+
+       ; clock select, no prescaler
+       in tmp1,TCCR1B
+       cbr tmp1,(1<<CS12)
+       cbr tmp1,(1<<CS11)
+       sbr tmp1,(1<<CS10)
+       out TCCR1B,tmp1
+
+       ret
+
+TIMER1_INIT_8:
+
+       ; clock select, prescaler 64
+       in tmp1,TCCR1B
+       cbr tmp1,(1<<CS12)
+       sbr tmp1,(1<<CS11)
+       cbr tmp1,(1<<CS10)
+       out TCCR1B,tmp1
+
+       ret
+
+TIMER1_INIT_64:
 
        ; clock select, prescaler 64
        in tmp1,TCCR1B
@@ -11,6 +33,28 @@ TIMER1_INIT:
 
        ret
 
+TIMER1_INIT_256:
+
+       ; clock select, prescaler 256
+       in tmp1,TCCR1B
+       sbr tmp1,(1<<CS12)
+       cbr tmp1,(1<<CS11)
+       cbr tmp1,(1<<CS10)
+       out TCCR1B,tmp1
+
+       ret
+
+TIMER1_INIT_1024:
+
+       ; clock select, prescaler 1024
+       in tmp1,TCCR1B
+       sbr tmp1,(1<<CS12)
+       cbr tmp1,(1<<CS11)
+       sbr tmp1,(1<<CS10)
+       out TCCR1B,tmp1
+
+       ret
+
 TIMER1_INT_ENABLE:
 
        ; overflow interrupt enable

diff --git a/monolyzer/uart.asm b/monolyzer/uart.asm
index fbfbf3d9342ff655be3bf5dfbac3461ca1a5ef80..fc2db5c9a600649ed49c9bdb3361090db1d487d3 100644 (file)
--- a/monolyzer/uart.asm
+++ b/monolyzer/uart.asm
@@ -4,7 +4,8 @@
 ; ifndef UART_BR_H
 .equ   UART_BR_H       = 0
 ; ifndef UART_BR_L
-.equ   UART_BR_L       = 25
+;.equ  UART_BR_L       = 25
+.equ   UART_BR_L       = 8
 
 UART_INIT: