fixed st and ld to sram - theoretically working now :)

diff --git a/beginners/season_junior.asm b/beginners/season_junior.asm
index e6a46067d459aaf6c6aa0bd249c0921370a2f84a..35d51d1f09b914b17b9b5bd1aa70594355f80047 100644 (file)
--- a/beginners/season_junior.asm
+++ b/beginners/season_junior.asm
@@ -28,14 +28,12 @@
 ; baudrate = clock freq / etu
 ; std smartcard etu: 372
 ; other smartcards: 625
-.define clock 8000000
-.define clk_h 4000000
-.define etu 625
-.define etu_h 312
-.define baudrate 5 ; UBRR value for 76800 bits/s (8mhz clock)
+.equ etu = 625
+.equ etu_h = 312
+.equ baudrate = 5 ; UBRR value for 76800 bits/s (8mhz clock)
 
 ; sizes
-.define uart_data_len 4
+.equ uart_data_len = 4
 
 ; names for registers
 .def tmp = r16
@@ -51,27 +49,25 @@
 .def mode = r26
 .def counter_l_tmp = r27
 .def counter_h_tmp = r28
-.def address_h = r31
-.def address_l = r30
 .def one = r1
 .def zero = r0
 
 ; state
-.define LOW (1<<0)
-.define LOW_F 1
-.define HIGH (1<<1)
-.define HIGH_F 2
+.equ LOW = (1<<0)
+.equ LOW_F = 1
+.equ HIGH = (1<<1)
+.equ HIGH_F = 2
 ; mode
-.define STUPID (1<<0) ; forward cam <-> card communication
-.define STUPID_F 1
-.define COOL (1<<1) ; send time (clocks) & state via uart
-.define COOL_F 2
-.define ELITE (1<<2) ; create bytes, maybe even whole command arrays
-.define ELITE_F 3
-.define GODLIKE (1<<3) ; filter and mask for commands to card - send rejected via uart only
-.define GODLIKE_F 4
-.define INCREDIBLE_HACK (1<<4) ; destroy all your hardware
-.define INCREDIBLE_HACK_F 5 
+.equ STUPID = (1<<0) ; forward cam <-> card communication
+.equ STUPID_F = 1
+.equ COOL = (1<<1) ; send time (clocks) & state via uart
+.equ COOL_F = 2
+.equ ELITE = (1<<2) ; create bytes, maybe even whole command arrays
+.equ ELITE_F = 3
+.equ GODLIKE = (1<<3) ; filter and mask for commands to card - send rejected via uart only
+.equ GODLIKE_F = 4
+.equ INCREDIBLE_HACK = (1<<4) ; destroy all your hardware
+.equ INCREDIBLE_HACK_F = 5 
 
 ; but there is only stupid and cool mode right now %)
 
@@ -162,7 +158,7 @@ ldi counter_h,0
 ldi state,HIGH ; .. as waiting for falling edge of start bit
 ldi state_m,0x03
 ldi mode,(STUPID|COOL)
-ldi address_h,0
+ldi ZH,0
 ldi tmp,1
 mov one,tmp
 ldi tmp,0
@@ -287,11 +283,11 @@ ret
 PREPARE_UART:
 
 ; write transfer data to sram
-ldi address_l,0x60
-st address_l+,counter_l
-st address_l+,counter_h
-st address_l+,overflow_counter
-st address_l+,state
+ldi ZL,0x60
+st Z+,counter_l
+st Z+,counter_h
+st Z+,overflow_counter
+st Z+,state
 
 ; enable uart data register empty interrupt
 sbi UCR,UDRIE
@@ -401,7 +397,6 @@ UART_OUT:
 cbi UCR,UDRIE
 
 ; init counter(s)
-mov address_l,zero
 mov tmp,zero
 
 ; send the data
@@ -436,7 +431,7 @@ UART_GS:
 ;
 
 ; read byte from memory and write via uart
-ld tmp1,address_l+
+ld tmp1,Z+
 out UDR,tmp1
 
 ; increment counter (maybe needed later)