*** empty log message ***

diff --git a/beginners/m128_tests.asm b/beginners/m128_tests.asm
new file mode 100644 (file)
index 0000000..413fa87
--- /dev/null
+++ b/beginners/m128_tests.asm
@@ -0,0 +1,184 @@
+.include "../include/m128def.inc"
+
+; interrupt vectors
+
+jmp RESET
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+jmp _INT4
+
+jmp _INT5
+
+jmp _INT6
+
+jmp _INT7
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+reti
+nop
+
+RESET:
+
+       ; init
+
+       ; set stackpointer
+       ldi r17,high(RAMEND)
+       out SPH,r17
+       ldi r17,low(RAMEND)
+       out SPL,r17
+
+       ; uart
+       ldi r17,(1<<TXEN0)
+       out UCSR0B,r17
+       ldi r17,(1<<UCSZ01|1<<UCSZ00)
+       sts UCSR0C,r17
+       ldi r17,0
+       sts UBRR0H,r17
+       ldi r17,25
+       out UBRR0L,r17
+
+       ; switches
+       ldi r17,(1<<PE4)|(1<<PE5)|(1<<PE6)|(1<<PE7)
+       out PORTE,r17
+       ldi r17,(1<<ISC41)|(1<<ISC51)|(1<<ISC61)|(1<<ISC71)
+       out EICRB,r17
+       ldi r17,(1<<INT4)|(1<<INT5)|(1<<INT6)|(1<<INT7)
+       out EIMSK,r17
+
+       ; misc
+       ldi r21,5
+       ldi r18,0x34
+
+       ; enable interrupts
+       sei
+
+; loop
+
+MAIN:
+
+       UART_T:
+               sbis UCSR0A,UDRE0
+               rjmp UART_T
+
+       out UDR0,r18
+
+       rjmp MAIN
+
+_INT4:
+       inc r18
+       
+       ldi r23,0
+       WAIT_1:
+               ldi r24,0
+               WAIT_2:
+                       ldi r25,0
+                       WAIT_3:
+                               inc r25
+                               cpi r25,0xff
+                               brne WAIT_3
+                       inc r24
+                       cpi r24,0xff
+                       brne WAIT_2
+               inc r23
+               cpi r23,0xff
+               brne WAIT_1
+
+       reti
+
+_INT5:
+       dec r18
+       reti
+
+_INT6:
+       add r18,r21
+       reti
+
+_INT7:
+       subi r18,5
+       reti
+