reti
; T1 OVF1
-reti
+rjmp T1_OVF_IR
; T0 OVF0
reti
; more init
ldi count,0
- ldi state,1
+ ldi state,0
; storage pointer
ldi ZL,low(STORAGE)
ldi ZH,high(STORAGE)
- ; counter
- ldi tmp1,0
- out TCNT1H,tmp1
- out TCNT1L,tmp1
-
; signal ready output
ldi uart_rxtx,0x72
rcall UART_TX
; external interrupt enable
- rcall INT0_IR_CONF
+ rcall INT0_IR_CONF_INIT
rcall INT0_IR_ENABLE
; global interrupt enable
SAMPLE:
; sample as long as there is storage capacity
- sbrc state,0
+ sbrs state,0
rjmp SAMPLE
- ; external interrupt enable
+ ; disable interrupts
rcall INT0_IR_DISABLE
+ rcall TIMER1_INT_DISABLE
; signal finish
ldi uart_rxtx,0x66
; reset storage pointer
ldi ZL,low(STORAGE)
ldi ZH,high(STORAGE)
- ldi count,0
+ ldi tmp1,0
+
+ ; transmit number of sampled words
+ mov uart_rxtx,count
+ rcall UART_TX
TRANSFER_LOOP:
rcall UART_TX
; count sent data
- add count,one
+ add tmp1,one
; check amount of sent data
- cpi count,110
+ cp tmp1,count
breq IDLE
rjmp TRANSFER_LOOP
; debug output
; cbi PORTD,3
- ; write timer value into sram
+ ; get timer value
in tmp1,TCNT1L
in tmp2,TCNT1H
+
+ ; check for initial or running state
+ cpi state,0
+ brne INT0_RUN
+
+ ; configure interrupt for running state
+ rcall INT0_IR_CONF_RUN
+ ldi state,1
+
+ ; reset timer and start ovf interrupt
+ ldi tmp1,0
+ out TCNT1H,tmp1
+ out TCNT1L,tmp1
+ rcall TIMER1_INT_ENABLE
+
+ rjmp EXIT_IR
+
+INT0_RUN:
+
+ ; write timer value into sram
st Z+,tmp2
st Z+,tmp1
reti
+T1_OVF_IR:
+
+ ; exit sampling
+ ldi state,0
+
+ reti
+
;
; sram
TIMER1_INIT:
; clock select, prescaler 8
- ldi tmp1,0x02
+ in tmp1,TCCR1B
+ cbr tmp1,(1<<CS12)
+ sbr tmp1,(1<<CS11)
+ cbr tmp1,(1<<CS10)
out TCCR1B,tmp1
ret
+TIMER1_INT_ENABLE:
+
+ ; overflow interrupt enable
+ in tmp1,TIMSK
+ sbr tmp1,(1<<TOIE1)
+ out TIMSK,tmp1
+
+ ret
+
+TIMER1_INT_DISABLE:
+
+ ; overflow interrupt disable
+ in tmp1,TIMSK
+ cbr tmp1,(1<<TOIE1)
+ out TIMSK,tmp1
+
+ ret
+