From: hackbard Date: Sat, 5 Jan 2008 16:15:26 +0000 (+0100) Subject: some bits changed during 24c3 (no comments!) :) X-Git-Url: https://hackdaworld.org/gitweb/?a=commitdiff_plain;h=dda42c5ae4c74fdb488ae105d2a493bce58483fa;p=my-code%2Ffpga.git some bits changed during 24c3 (no comments!) :) --- diff --git a/fx2/fx2.c b/fx2/fx2.c index 49f0da5..0ba6db9 100644 --- a/fx2/fx2.c +++ b/fx2/fx2.c @@ -130,29 +130,49 @@ void slave_fifo_init() { /* initialization of the slave fifo, used by external logic (the fpga) * to do usb communication with the host */ - /* set bit 0 and 1 - fifo slave config */ - IFCONFIG|=0x03; + /* enable dyn_out and enhanced packet handling (p. 189) */ + REVCTL=0x03; SYNCDELAY; - /* async mode */ - IFCONFIG|=0x04; + /* internal 48 mhz clock, async, slave fifo */ + IFCONFIG=0xcb; SYNCDELAY; - /* p. 180: must be set to 1 */ - REVCTL|=((1<<0)|(1<<1)); - SYNCDELAY; - - /* 8 bit fifo to all endpoints + /* endpoint setup: * - * ('or' of all these bits define port d functionality) + * ep2: bulk out 2x512 + * ep4: bulk out 2x512 + * ep6: bulk in 2x512 + * ep8: bulk in 2x512 */ - EP2FIFOCFG&=~(1<<0); + EP2CFG=0xa2; + EP4CFG=0xa0; + EP6CFG=0xc2; + EP8CFG=0xc0; SYNCDELAY; - EP4FIFOCFG&=~(1<<0); + + /* reset the fifo */ + FIFORESET=0x80; /* nak all transfers */ SYNCDELAY; - EP6FIFOCFG&=~(1<<0); + FIFORESET=0x02; /* reset ep2 */ + SYNCDELAY; + FIFORESET=0x04; /* reset ep4 */ + SYNCDELAY; + FIFORESET=0x06; /* reset ep6 */ SYNCDELAY; - EP8FIFOCFG&=~(1<<0); + FIFORESET=0x08; /* reset ep8 */ + SYNCDELAY; + FIFORESET=0x00; /* restore normal operation */ + SYNCDELAY; + + /* 8 bit fifo to all endpoints */ + EP2FIFOCFG=; + SYNCDELAY; + EP4FIFOCFG=; + SYNCDELAY; + EP6FIFOCFG=; + SYNCDELAY; + EP8FIFOCFG=; SYNCDELAY; /* default indexed flag configuration: @@ -164,33 +184,6 @@ void slave_fifo_init() { * todo: -> fixed configuration */ - /* endpoint configuration: - * - * ep2: bulk out 4x512 - * ep6: bulk in 4x512 - * - * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512 - * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512 - */ - EP2CFG=0xa0; - SYNCDELAY; - EP4CFG&=(~0x80); - SYNCDELAY; - EP6CFG=0xe0; - SYNCDELAY; - EP8CFG&=(~0x80); - SYNCDELAY; - - /* reset the fifo */ - FIFORESET=0x80; /* nak all transfers */ - SYNCDELAY; - FIFORESET=0x02; /* reset ep2 */ - SYNCDELAY; - FIFORESET=0x06; /* reset ep6 */ - SYNCDELAY; - FIFORESET=0x00; /* restore normal operation */ - SYNCDELAY; - /* auto in/out, no cpu interaction! auto in len = 512 */ EP2FIFOCFG|=(1<<4); SYNCDELAY; @@ -216,7 +209,7 @@ void ep1_init() { */ /* arm ep1out, clear ep1out and ep1in stall bit */ - EP1OUTBC=1; + EP1OUTBC=0; EP1OUTCS&=~STALL; EP1INCS&=~STALL;