#define BANK2 0x82000000
#define BANK_SIZE 0x00100000
#define BOOTLOADER 0x7fffe000
-#define BL_SIZE 0x00000800
+#define BL_SIZE 0x00002000
/* flash cmd addresses - flash[0-18] <--> arm[1-19]*/
#define B0F555 (*((volatile unsigned long *)(BANK0|0xaaa))) // 0x555
MEMMAP=memtype;
}
+void pll_init(void) {
+
+ /* configuration */
+ PLLCFG=0x02; // multiplier = 2
+ PLLCON=0x03; // enable and set as clk source for the lpc
+ /* feed sequence */
+ PLLFEED=0xaa;
+ PLLFEED=0x55;
+ /* wait for lock */
+ while(!(PLLSTAT&(1<<10)))
+ continue;
+}
+
void uart0_init(void) {
PINSEL0=0x05; // pin select -> tx, rx
UART0_FCR=0x07; // enable fifo
UART0_LCR=0x83; // set dlab + word length
- //UART0_DLL=0x10; // br: 9600 @ 10/4 mhz
UART0_DLL=0x04; // br: 38400 @ 10/4 mhz
UART0_DLM=0x00;
UART0_LCR=0x03; // unset dlab
/* memory mapping of interrupt vectors to static ram */
//mmap_init(MMAP_RAM);
+
+ /* pll initialization */
+ pll_init();
/* uart initialization */
uart0_init();