prepare for interrupt support in the next few days
[my-code/arm.git] / betty / startup.s
index 7cf1e10..d393d32 100644 (file)
 .arm
 
        # exception handling must go to the very beginning
-
-       b handler_reset
-       b interrupt_handler_undef_instruction
-       b interrupt_handler_soft_ir
-       b interrupt_handler_prefetch_abort
-       b interrupt_handler_data_abort
+       #
+       # concerning irq:
+       #  - the ldr is at 0x18
+       #  - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+       #  - substract 0xff0 => 0xfffff030
+       #  - that's the vectored address register
+       #  - the vic put in there the address of our service routine
+
+       ldr pc, handler_reset
+       ldr pc, handler_undef_instruction
+       ldr pc, handler_soft_ir
+       ldr pc, handler_prefetch_abort
+       ldr pc, handler_data_abort
        nop
-       b interrupt_handler_irq
-       b interrupt_handler_fiq
+       ldr pc, [pc, #-0xff0]
+       ldr pc, handler_fiq
+
+handler_reset: .word handle_reset
+handler_undef_instruction: .word interrupt_handler_undef_instruction
+handler_soft_ir: .word interrupt_handler_soft_ir
+handler_prefetch_abort: .word interrupt_handler_prefetch_abort
+handler_data_abort: .word interrupt_handler_data_abort
+handler_fiq: .word interrupt_handler_fiq
 
        # reset handling goes here
 
-handler_reset:
+handle_reset:
 
        # init stack pointer for each mode + set stack limit
 
@@ -94,12 +108,15 @@ handler_reset:
        ldr r0, =stack_limit
        mov sl, r0
 
-       # copy data section
+       # copy data section (only if we are in flash <=> _etext != _data)
 
        ldr r1, =_etext
        ldr r2, =_data
        ldr r3, =_edata
 
+       cmp r1, r2
+       beq start_of_c_code
+
 copy_data_loop:
 
        cmp r2, r3
@@ -109,6 +126,8 @@ copy_data_loop:
 
        # jump to c code
 
+start_of_c_code:
+
        adr lr, loop_forever
        mov r0, #0
        mov r1, #0