+ # exception handling must go to the very beginning
+ #
+ # concerning irq:
+ # - the ldr is at 0x18
+ # - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+ # - substract 0xff0 => 0xfffff030
+ # - that's the vectored address register
+ # - the vic put in there the address of our service routine
+
+ ldr pc, handler_reset
+ ldr pc, handler_undef_instruction
+ ldr pc, handler_soft_ir
+ ldr pc, handler_prefetch_abort
+ ldr pc, handler_data_abort
+ nop
+ ldr pc, [pc, #-0xff0]
+ ldr pc, handler_fiq
+
+handler_reset: .word handle_reset
+handler_undef_instruction: .word interrupt_handler_undef_instruction
+handler_soft_ir: .word interrupt_handler_soft_ir
+handler_prefetch_abort: .word interrupt_handler_prefetch_abort
+handler_data_abort: .word interrupt_handler_data_abort
+handler_fiq: .word interrupt_handler_fiq
+
+ # reset handling goes here
+
+handle_reset:
+
+ # init stack pointer for each mode + set stack limit