prepare for interrupt support in the next few days

[my-code/arm.git] / betty / startup.s

diff --git a/betty/startup.s b/betty/startup.s
index d6b0184..d393d32 100644 (file)
--- a/betty/startup.s
+++ b/betty/startup.s
@@ -49,6 +49,13 @@
 .arm
 
        # exception handling must go to the very beginning
+       #
+       # concerning irq:
+       #  - the ldr is at 0x18
+       #  - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+       #  - substract 0xff0 => 0xfffff030
+       #  - that's the vectored address register
+       #  - the vic put in there the address of our service routine
 
        ldr pc, handler_reset
        ldr pc, handler_undef_instruction
@@ -56,7 +63,7 @@
        ldr pc, handler_prefetch_abort
        ldr pc, handler_data_abort
        nop
-       ldr pc, handler_irq
+       ldr pc, [pc, #-0xff0]
        ldr pc, handler_fiq
 
 handler_reset: .word handle_reset
@@ -64,7 +71,6 @@ handler_undef_instruction: .word interrupt_handler_undef_instruction
 handler_soft_ir: .word interrupt_handler_soft_ir
 handler_prefetch_abort: .word interrupt_handler_prefetch_abort
 handler_data_abort: .word interrupt_handler_data_abort
-handler_irq: .word interrupt_handler_irq
 handler_fiq: .word interrupt_handler_fiq
 
        # reset handling goes here
@@ -102,12 +108,15 @@ handle_reset:
        ldr r0, =stack_limit
        mov sl, r0
 
-       # copy data section
+       # copy data section (only if we are in flash <=> _etext != _data)
 
        ldr r1, =_etext
        ldr r2, =_data
        ldr r3, =_edata
 
+       cmp r1, r2
+       beq start_of_c_code
+
 copy_data_loop:
 
        cmp r2, r3
@@ -117,6 +126,8 @@ copy_data_loop:
 
        # jump to c code
 
+start_of_c_code:
+
        adr lr, loop_forever
        mov r0, #0
        mov r1, #0