X-Git-Url: https://hackdaworld.org/gitweb/?p=my-code%2Farm.git;a=blobdiff_plain;f=betty%2Fstartup.s;h=18006aabf364f4cd610f711c83990ffc6756c02d;hp=af87f6e37c9a62c43f14befb4dfd607e8f21f0d0;hb=HEAD;hpb=26b834d1801d8453bb25b6b427a6b6c3b131cf57

diff --git a/betty/startup.s b/betty/startup.s
index af87f6e..18006aa 100644
--- a/betty/startup.s
+++ b/betty/startup.s
@@ -41,6 +41,8 @@
 .equ	fiq_disable,	0x40
 .equ	irq_disable,	0x80
 
+.equ	vic_vect_addr,	0xfffff030
+
 #
 # the startup code
 #
@@ -49,26 +51,37 @@
 .arm
 
 	# exception handling must go to the very beginning
-
-	b handler_reset
-	b handler_undef_instruction
-	b handler_soft_ir
-	b handler_prefetch_abort
-	b handler_data_abort
+	#
+	# concerning irq:
+	#  - the ldr is at 0x18
+	#  - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+	#  - substract 0xff0 => 0xfffff030
+	#  - that's the vectored address register
+	#  - the vic put in there the address of our service routine
+
+exception_vectors:
+
+	ldr pc, handler_reset
+	ldr pc, handler_undef_instruction
+	ldr pc, handler_soft_ir
+	ldr pc, handler_prefetch_abort
+	ldr pc, handler_data_abort
 	nop
-	b handler_irq
-	b handler_fiq
-
-	handler_undef_instruction: .word interrupt_handler_undef_instruction
-	handler_soft_ir: .word interrupt_handler_soft_ir
-	handler_prefetch_abort: .word interrupt_handler_prefetch_abort
-	handler_data_abort: .word interrupt_handler_data_abort
-	handler_irq: .word interrupt_handler_irq
-	handler_fiq: .word interrupt_handler_fiq
+	ldr pc, [pc, #-0xff0]
+	#ldr pc, handler_irq
+	ldr pc, handler_fiq
+
+handler_reset: .word handle_reset
+handler_undef_instruction: .word interrupt_handler_undef_instruction
+handler_soft_ir: .word interrupt_handler_soft_ir
+handler_prefetch_abort: .word interrupt_handler_prefetch_abort
+handler_data_abort: .word interrupt_handler_data_abort
+handler_irq: .word vic_vect_addr
+handler_fiq: .word interrupt_handler_fiq
 
 	# reset handling goes here
 
-handler_reset:
+handle_reset:
 
 	# init stack pointer for each mode + set stack limit
 
@@ -101,21 +114,41 @@ handler_reset:
 	ldr r0, =stack_limit
 	mov sl, r0
 
-	# copy data section
+	# enable irq and fiq
+	msr cpsr_c, #mode_system
+
+	# copy data section (only if we are in flash <=> _etext != _data)
 
 	ldr r1, =_etext
 	ldr r2, =_data
 	ldr r3, =_edata
 
+	cmp r1, r2
+	beq copy_exception_vectors
+
 copy_data_loop:
 
 	cmp r2, r3
 	ldrlo r0, [r1], #4
 	strlo r0, [r2], #4
 	blo copy_data_loop
+	b start_of_c_code
+
+	# copy exception vectors (only if we are in ram <=> _etext = _data)
+
+copy_exception_vectors:
+
+	mov r0, #sram_addr
+	ldr r1, =exception_vectors
+	ldmia r1!, {r2-r9}
+	stmia r0!, {r2-r9}
+	ldmia r1!, {r2-r8}
+	stmia r0!, {r2-r8}
 
 	# jump to c code
 
+start_of_c_code:
+
 	adr lr, loop_forever
 	mov r0, #0
 	mov r1, #0