; main file of the monolyzer project
;
; author: hackbard@hackdaworld.org
;

; device specific definition file
.include "../include/tn2313def.inc"

; defines
.def	zero		= r1
.def	one		= r2
.def	tmp1		= r16
.def	tmp2		= r17
.def	uart_rxtx	= r18
.def	bcount		= r19
.def	scount		= r20
.def	data		= r21
.def	state		= r22

;
; interrupts
;

; RESET
rjmp INIT

; INT0
reti

; INT1
reti

; T1 CAPT1
reti

; T1 COMP A
reti

; T1 OVF1
reti

; T0 OVF0
rjmp T0_OVF

; UART RX
rjmp UART_RECEIVE

; UART UDRE
reti

; UART TX
reti

; ANA COMP
reti

; PCINT
reti

; T1 COMP B
reti

; T0 COMP A
reti

; T0 COMP B
reti

; USI START
reti

; USI OVF
reti

; EE READY
reti

; WDT OVF
reti

;
; init and main code
;

RESET:
INIT:

	; gio port init
	rcall PORT_INIT

	; timer0 init
	rcall TIMER0_INIT

	; uart init
	rcall UART_INIT

	; zero and one initialization
	ldi tmp1,0
	mov zero,tmp1
	ldi tmp1,1
	mov one,tmp1

	; set stackpointer
	ldi tmp1,low(RAMEND)
	out SPL,tmp1

	; more init
	ldi bcount,0
	ldi scount,0
	ldi data,0x00
	ldi state,1

	; storage pointer
	ldi ZL,low(STORAGE)
	ldi ZH,high(STORAGE)

	; signal ready output
	ldi uart_rxtx,0x72
	rcall UART_TX

	; global interrupt enable
	sei 

MAIN:

WAIT_FOR_HIGH:

	; start as soon as we get a high signal
	in tmp1,PORTB
	sbrs tmp1,0
	rjmp WAIT_FOR_HIGH

	; timer0 interrupt enable
	rcall TIMER0_INT_INIT
	
SAMPLE:

	; sample as long as there is storage capacity
	sbrc state,0
	rjmp SAMPLE

	; timer0 interrupt disable
	rcall TIMER0_INT_END

	; signal finish
	ldi uart_rxtx,0x66
	rcall UART_TX

IDLE:

	; wait for commands via uart
	rcall UART_RX

	; decode instruction
	cpi uart_rxtx,0x52
	breq RESET
	cpi uart_rxtx,0x54
	breq TRANSFER

	rjmp IDLE

TRANSFER:

	; reset storage pointer
	ldi ZL,low(STORAGE)
	ldi ZH,high(STORAGE)
	ldi scount,0

TRANSFER_LOOP:

	; transmit storage
	ld uart_rxtx,Z+
	rcall UART_TX

	; count sent data
	add scount,one

	; check amount of sent data
	cpi scount,128
	breq IDLE

	rjmp TRANSFER_LOOP

; include subroutines
.include "port.asm"
.include "timer.asm"
.include "uart.asm"

;
; interrupt routines
;

T0_OVF:

	; debug output
	; cbi PORTD,3

	; read port
	in tmp1,PORTB
	sbrc tmp1,0
	add data,one

	; increase and check bit counter
	add bcount,one
	cpi bcount,8
	brne EXIT_T0_OVF
	
	; store another byte into sram
	st Z+,data
	ldi bcount,0
	add scount,one

	; check for left capacity
	cpi scount,128
	brne EXIT_T0_OVF
	ldi state,0

	; debug output
	; sbi PORTD,3

EXIT_T0_OVF:

	; shift data bits
	; in any case => there is always a zero at lsb
	lsl data
	
	reti

UART_RECEIVE:

	reti


;
; sram
;

.dseg

STORAGE: .byte 128