; main file of the monolyzer project
;
; author: hackbard@hackdaworld.org
;

; device specific definition file
.include "../include/tn2313def.inc"

; defines
.def	zero		= r1
.def	one		= r2
.def	tmp1		= r16
.def	tmp2		= r17
.def	uart_rxtx	= r18
.def	count		= r19
.def	state		= r20
.def	scount		= r21
.def	input		= r22
.def	save		= r23

;.define FLOODME
;.define S_FLOODME

;
; interrupts
;

; RESET
rjmp INIT

; INT0
rjmp INT0_IR

; INT1
reti

; T1 CAPT1
reti

; T1 COMP A
reti

; T1 OVF1
rjmp T1_OVF_IR

; T0 OVF0
reti

; UART RX
reti

; UART UDRE
reti

; UART TX
reti

; ANA COMP
reti

; PCINT
reti

; T1 COMP B
reti

; T0 COMP A
reti

; T0 COMP B
reti

; USI START
reti

; USI OVF
reti

; EE READY
reti

; WDT OVF
reti

;
; init and main code
;

RESET:
INIT:

	; gio port init
	rcall PORT_INIT

	; timer1 init
	rcall TIMER1_INIT_64

	; uart init
	rcall UART_INIT

	; zero and one initialization
	ldi tmp1,0
	mov zero,tmp1
	ldi tmp1,1
	mov one,tmp1

	; set stackpointer
	ldi tmp1,low(RAMEND)
	out SPL,tmp1

	; more init
	ldi count,0
	ldi state,0

	; storage pointer
	ldi ZL,low(STORAGE)
	ldi ZH,high(STORAGE)

	ldi scount,0
	ldi tmp1,0x23
INIT_STORAGE:
	; init storage
	st Z+,tmp1
	st Z+,tmp1
	add scount,one
	cpi scount,55
	brne INIT_STORAGE

	; storage pointer again
	ldi ZL,low(STORAGE)
	ldi ZH,high(STORAGE)

	; signal ready output
	ldi uart_rxtx,0x72
	rcall UART_TX

.ifdef FLOODME
DEBUG_PORT:
	;rcall UART_RX
	ldi scount,0
DEBUG_PORT_LOOP:
	lsl uart_rxtx
	in tmp1,PIND
	sbrc tmp1,2
	add uart_rxtx,one
	add scount,one
	cpi scount,8
	brne DEBUG_PORT_LOOP
	rcall UART_TX
	rjmp DEBUG_PORT
.endif

.ifdef S_FLOODME
DEBUG_PORT:
	ldi uart_rxtx,0x30
	in tmp1,PIND
	sbrc tmp1,2
	add uart_rxtx,one
	rcall UART_TX
	rjmp DEBUG_PORT
.endif
	; enable interrupts
	rcall INT0_IR_CONF_R
	rcall INT0_IR_ENABLE

	; global interrupt enable
	sei 

MAIN:

SAMPLE:

	; sample as long as there is storage capacity and signal
	cpi state,10
	brne SAMPLE

	; signal finish
	ldi uart_rxtx,0x66
	rcall UART_TX

IDLE:

	; wait for commands via uart
	rcall UART_RX

	; decode instruction
	cpi uart_rxtx,0x72
	breq RESET
	cpi uart_rxtx,0x74
	breq TRANSFER
	cpi uart_rxtx,0x73
	breq SINGLE_SAMPLE

	rjmp IDLE

SINGLE_SAMPLE:

	; sample port d pin 2 and output via uart
	ldi uart_rxtx,0x30
	in tmp2,PIND
	sbrc tmp2,2
	ldi uart_rxtx,0x31
	rcall UART_TX
	rjmp IDLE

TRANSFER:

	; reset storage pointer
	ldi ZL,low(STORAGE)
	ldi ZH,high(STORAGE)
	ldi scount,1

	; transmit number of sampled words
	mov uart_rxtx,count
	rcall UART_TX

TRANSFER_LOOP:

	; send data and counter
	ld uart_rxtx,Z+
	rcall UART_TX
	ld uart_rxtx,Z+
	rcall UART_TX

	; count sent data
	add scount,one

	; check amount of data
	cpi scount,56
	breq IDLE

	rjmp TRANSFER_LOOP

; include subroutines
.include "port.asm"
.include "timer.asm"
.include "uart.asm"

;
; interrupt routines
;

INT0_IR:

	in save,SREG

	cli

	; get timer value
	in tmp1,TCNT1L
	in tmp2,TCNT1H

	; reset timer
	ldi tmp1,0
	out TCNT1H,tmp1
	out TCNT1L,tmp1

	; check for running state
	cpi state,5
	breq INT0_RUN

	; reconfigure int0
	rcall INT0_IR_CONF_FR
	ldi state,5
	rcall TIMER1_INT_ENABLE

	rjmp LEAVE_INT0_IR

INT0_RUN:

	; write timer value into sram
	st Z+,tmp2
	st Z+,tmp1

	; inc counter
	add count,one
	
	; check for left capacity
	cpi count,55
	brne LEAVE_INT0_IR

	; indicate end of 'c'apacity
	ldi uart_rxtx,0x63
	rcall UART_TX

	; exit sampling
	ldi state,10

	; leave all interrupts cleared
	rjmp EXIT_INT0_IR

LEAVE_INT0_IR:

	sei

EXIT_INT0_IR:

	out SREG,save

	reti

T1_OVF_IR:

	in save,SREG

	cli

	; indicate 'o'verflow end
	ldi uart_rxtx,0x6f
	rcall UART_TX

	; exit sampling
	ldi state,10

	out SREG,save

	reti

;
; sram
;

.dseg

STORAGE: .byte 110