X-Git-Url: https://hackdaworld.org/gitweb/?p=my-code%2Fatmel.git;a=blobdiff_plain;f=monolyzer%2Fmain.asm;fp=monolyzer%2Fmain.asm;h=bcc6c1c87b1ced5d2b0adff680ac0d58cbe830fe;hp=73aaf5ec749b186a116f9ac2c12f0396e2b6be4e;hb=1117f788c441bc3d8caf90e5fb883e11696e1757;hpb=96c049990876625353c38ab10fd8bf0e698b3973

diff --git a/monolyzer/main.asm b/monolyzer/main.asm
index 73aaf5e..bcc6c1c 100644
--- a/monolyzer/main.asm
+++ b/monolyzer/main.asm
@@ -12,10 +12,8 @@
 .def	tmp1		= r16
 .def	tmp2		= r17
 .def	uart_rxtx	= r18
-.def	bcount		= r19
-.def	scount		= r20
-.def	data		= r21
-.def	state		= r22
+.def	count		= r19
+.def	state		= r20
 
 ;
 ; interrupts
@@ -25,7 +23,7 @@
 rjmp INIT
 
 ; INT0
-reti
+rjmp INT0_IR
 
 ; INT1
 reti
@@ -40,10 +38,10 @@ reti
 reti
 
 ; T0 OVF0
-rjmp T0_OVF
+reti
 
 ; UART RX
-rjmp UART_RECEIVE
+reti
 
 ; UART UDRE
 reti
@@ -88,8 +86,8 @@ INIT:
 	; gio port init
 	rcall PORT_INIT
 
-	; timer0 init
-	rcall TIMER0_INIT
+	; timer1 init
+	rcall TIMER1_INIT
 
 	; uart init
 	rcall UART_INIT
@@ -105,42 +103,39 @@ INIT:
 	out SPL,tmp1
 
 	; more init
-	ldi bcount,0
-	ldi scount,0
-	ldi data,0x00
+	ldi count,0
 	ldi state,1
 
 	; storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
 
+	; counter
+	ldi tmp1,0
+	out TCNT1H,tmp1
+	out TCNT1L,tmp1
+
 	; signal ready output
 	ldi uart_rxtx,0x72
 	rcall UART_TX
 
+	; external interrupt enable
+	rcall INT0_IR_CONF
+	rcall INT0_IR_ENABLE
+
 	; global interrupt enable
 	sei 
 
 MAIN:
 
-WAIT_FOR_HIGH:
-
-	; start as soon as we get a high signal
-	in tmp1,PORTB
-	sbrs tmp1,0
-	rjmp WAIT_FOR_HIGH
-
-	; timer0 interrupt enable
-	rcall TIMER0_INT_INIT
-	
 SAMPLE:
 
 	; sample as long as there is storage capacity
 	sbrc state,0
 	rjmp SAMPLE
 
-	; timer0 interrupt disable
-	rcall TIMER0_INT_END
+	; external interrupt enable
+	rcall INT0_IR_DISABLE
 
 	; signal finish
 	ldi uart_rxtx,0x66
@@ -164,7 +159,7 @@ TRANSFER:
 	; reset storage pointer
 	ldi ZL,low(STORAGE)
 	ldi ZH,high(STORAGE)
-	ldi scount,0
+	ldi count,0
 
 TRANSFER_LOOP:
 
@@ -173,10 +168,10 @@ TRANSFER_LOOP:
 	rcall UART_TX
 
 	; count sent data
-	add scount,one
+	add count,one
 
 	; check amount of sent data
-	cpi scount,128
+	cpi count,110
 	breq IDLE
 
 	rjmp TRANSFER_LOOP
@@ -190,44 +185,32 @@ TRANSFER_LOOP:
 ; interrupt routines
 ;
 
-T0_OVF:
+INT0_IR:
 
 	; debug output
 	; cbi PORTD,3
 
-	; read port
-	in tmp1,PORTB
-	sbrc tmp1,0
-	add data,one
-
-	; increase and check bit counter
-	add bcount,one
-	cpi bcount,8
-	brne EXIT_T0_OVF
-	
-	; store another byte into sram
-	st Z+,data
-	ldi bcount,0
-	add scount,one
+	; write timer value into sram
+	in tmp1,TCNT1L
+	in tmp2,TCNT1H
+	st Z+,tmp2
+	st Z+,tmp1
+
+	; inc counter
+	add count,one
 
 	; check for left capacity
-	cpi scount,128
-	brne EXIT_T0_OVF
+	cpi count,55
+	brne EXIT_IR
+
+	; exit sampling
 	ldi state,0
 
+EXIT_IR:
+
 	; debug output
 	; sbi PORTD,3
 
-EXIT_T0_OVF:
-
-	; shift data bits
-	; in any case => there is always a zero at lsb
-	lsl data
-	
-	reti
-
-UART_RECEIVE:
-
 	reti
 
 
@@ -237,6 +220,5 @@ UART_RECEIVE:
 
 .dseg
 
-STORAGE: .byte 128
-
+STORAGE: .byte 110