--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"1200def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S1200\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-Mail :avr@atmel.com\r
+;* Target MCU :AT90S1200\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* \r
+;* The Register names are represented by their hexadecimal addresses.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S1200\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ GIMSK =$3b\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ ACSR =$08\r
+\r
+;***** Bit Definitions\r
+\r
+.equ INT0 =6\r
+\r
+.equ TOIE0 =1\r
+\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ XRAMEND =$0\r
+.equ E2END =$3F\r
+.equ FLASHEND=$1FF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ OVF0addr=$002 ;Overflow0 Interrupt Vector Address\r
+.equ ACIaddr =$003 ;Analog Comparator Interrupt Vector Address\r
+\r
+.def ZL =r30\r
+.def ZH =r31\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"2313def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S2313\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-Mail :avr@atmel.com\r
+;* Target MCU :AT90S2313\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* \r
+;* The Register names are represented by their hexadecimal addresses.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S2313\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+\r
+\r
+;***** Bit Definitions\r
+.equ SP7 =7\r
+.equ SP6 =6\r
+.equ SP5 =5\r
+.equ SP4 =4\r
+.equ SP3 =3\r
+.equ SP2 =2\r
+.equ SP1 =1\r
+.equ SP0 =0\r
+\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ TICIE =3\r
+.equ TOIE0 =1\r
+\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$7F\r
+.equ FLASHEND=$3FF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1addr =$004 ;Output Compare1 Interrupt Vector Address\r
+.equ OVF1addr=$005 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$006 ;Overflow0 Interrupt Vector Address\r
+.equ URXCaddr=$007 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$008 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$009 ;UART Transmit Complete Interrupt Vector Address\r
+.equ ACIaddr =$00a ;Analog Comparator Interrupt Vector Address\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"2323def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S2323\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-Mail :avr@atmel.com\r
+;* Target MCU :AT90S2323\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* \r
+;* The Register names are represented by their hexadecimal addresses.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S2323\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+\r
+;***** Bit Definitions\r
+\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT0 =6\r
+.equ INTF0 =6\r
+\r
+.equ TOIE0 =1\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$7F\r
+.equ FLASHEND=$3FF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ OVF0addr=$002 ;Overflow0 Interrupt Vector Address\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"2333def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S2333\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S2333\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***** Specify Device\r
+.device AT90S2333\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SP =$3d\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1H =$2b\r
+.equ OCR1L =$2a\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UBRR =$09\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ UBRRH =$03\r
+\r
+\r
+;***** Bit Definitions\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+\r
+.equ TOIE1 =7\r
+.equ OCIE1 =6\r
+.equ TICIE1 =3\r
+.equ TOIE0 =1\r
+\r
+.equ TOV1 =7\r
+.equ OCF1 =6\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ COM11 =7\r
+.equ COM10 =6\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ MPCM =0\r
+\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+.equ ACD =7\r
+.equ AINBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ ADCBG =6\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$7F\r
+.equ FLASHEND=$3FF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$004 ;Output Compare1A Interrupt Vector Address\r
+.equ OVF1addr=$005 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$006 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$007 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$008 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$009 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00a ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr =$00b ;ADC Interrupt Vector Address\r
+.equ ERDYaddr =$00c ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$00d ;Analog Comparator Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"2343def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S2343\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-Mail :avr@atmel.com\r
+;* Target MCU :AT90S2343\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* \r
+;* The Register names are represented by their hexadecimal addresses.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S2343\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+\r
+;***** Bit Definitions\r
+\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT0 =6\r
+.equ INTF0 =6\r
+\r
+.equ TOIE0 =1\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$7F\r
+.equ FLASHEND=$3FF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ OVF0addr=$002 ;Overflow0 Interrupt Vector Address\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"4414def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S4414\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S4414\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S4414\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ WDTCR =$21\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+\r
+\r
+;***** Bit Definitions\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TICIE1 =3\r
+.equ TOIE0 =1\r
+\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+\r
+.equ SRE =7\r
+.equ SRW =6\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDDE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$15F ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$FFFF\r
+.equ E2END =$FF\r
+.equ FLASHEND=$7FF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$004 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$005 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$006 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$007 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$008 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$009 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00a ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00b ;UART Transmit Complete Interrupt Vector Address\r
+.equ ACIaddr =$00c ;Analog Comparator Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"4433def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S4433\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S4433\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***** Specify Device\r
+.device AT90S4433\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SP =$3d\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1H =$2b\r
+.equ OCR1L =$2a\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UBRR =$09\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ UBRRH =$03\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+\r
+.equ TOIE1 =7\r
+.equ OCIE1 =6\r
+.equ TICIE1 =3\r
+.equ TOIE0 =1\r
+\r
+.equ TOV1 =7\r
+.equ OCF1 =6\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ COM11 =7\r
+.equ COM10 =6\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ MPCM =0\r
+\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+.equ ACD =7\r
+.equ AINBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ ADCBG =6\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$FF\r
+.equ FLASHEND=$7FF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$004 ;Output Compare1A Interrupt Vector Address\r
+.equ OVF1addr=$005 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$006 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$007 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$008 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$009 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00a ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr =$00b ;ADC Interrupt Vector Address\r
+.equ ERDYaddr =$00c ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$00d ;Analog Comparator Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"4434def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S4434\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S4434\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S4434\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+;***** Bit Definitions\r
+\r
+;MCUSR\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+;TIMSK\r
+.equ OCIE2 =7\r
+.equ TOIE2 =6\r
+.equ TICIE1 =5\r
+.equ OCIE1A =4\r
+.equ OCIE1B =3\r
+.equ TOIE1 =2\r
+.equ TOIE0 =0\r
+\r
+;TIFR\r
+.equ OCF2 =7\r
+.equ TOV2 =6\r
+.equ ICF1 =5\r
+.equ OCF1A =4\r
+.equ OCF1B =3\r
+.equ TOV1 =2\r
+.equ TOV0 =0\r
+\r
+;MCUCR\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+;USR\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+;UCR\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$15F ;Last On-Chip SRAM location\r
+.equ XRAMEND =$15F\r
+.equ E2END =$FF\r
+.equ FLASHEND=$7FF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ;Timer2 compare match Vector Address\r
+.equ OVF2addr=$004 ;Timer2 overflow Vector Address\r
+.equ ICP1addr=$005 ;Timer1 Input Capture Vector Address\r
+.equ OC1Aaddr=$006 ;Timer1 Output Compare A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ;Timer1 Output Compare B Interrupt Vector Address\r
+.equ OVF1addr=$008 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00A ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$00B ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00C ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00D ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00E ;ADC Conversion Complete Interrupt Vector Address\r
+.equ ERDYaddr=$00F ;EEPROM Write Complete Interrupt Vector Address\r
+.equ ACIaddr =$010 ;Analog Comparator Interrupt Vector Address
\ No newline at end of file
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"8515def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S8515\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S8515\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S8515\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ WDTCR =$21\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+\r
+;***** Bit Definitions\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+;TIMSK\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TICIE1 =3\r
+.equ TOIE0 =1\r
+\r
+;TIFR\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+\r
+;MCUCR\r
+.equ SRE =7\r
+.equ SRW =6\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+;USR\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+;UCR\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$25F ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$FFFF\r
+.equ E2END =$1FF\r
+.equ FLASHEND=$FFF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$004 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$005 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$006 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$007 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$008 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$009 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00a ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00b ;UART Transmit Complete Interrupt Vector Address\r
+.equ ACIaddr =$00c ;Analog Comparator Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"8534def.inc"\r
+;* Title :Register/Bit Definitions for the AT90C8534\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90C8534\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;*\r
+;***** Specify Device\r
+.device AT90C8534\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1 =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ GIPR =$10\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+;***** Bit Definitions\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+;GIPR\r
+.equ IPIN1 =3\r
+.equ IPIN0 =2\r
+\r
+;TIMSK\r
+.equ TOIE1 =2\r
+.equ TOIE0 =0\r
+\r
+;TIFR\r
+.equ TOV1 =2\r
+.equ TOV0 =0\r
+\r
+;MCUCR\r
+.equ SE =6\r
+.equ SM =5\r
+.equ ISC1 =2\r
+.equ ISC0 =0\r
+\r
+;TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;ADMUX\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$15f\r
+.equ XRAMEND =$15F\r
+.equ E2END =$1FF\r
+.equ FLASHEND=$FFF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OVF1addr=$003 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$004 ;Overflow0 Interrupt Vector Address\r
+.equ ADCCaddr =$005 ;ADC Interrupt Vector Address\r
+.equ ERDYaddr =$006 ;EEPROM Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"8535def.inc"\r
+;* Title :Register/Bit Definitions for the AT90S8535\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :AT90S8535\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device AT90S8535\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+\r
+;***** Bit Definitions\r
+;MCUSR\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+;TIMSK\r
+.equ OCIE2 =7\r
+.equ TOIE2 =6\r
+.equ TICIE1 =5\r
+.equ OCIE1A =4\r
+.equ OCIE1B =3\r
+.equ TOIE1 =2\r
+.equ TOIE0 =0\r
+\r
+;TIFR\r
+.equ OCF2 =7\r
+.equ TOV2 =6\r
+.equ ICF1 =5\r
+.equ OCF1A =4\r
+.equ OCF1B =3\r
+.equ TOV1 =2\r
+.equ TOV0 =0\r
+\r
+;MCUCR\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+;USR\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+;RXCIE\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$25F ;Last On-Chip SRAM location\r
+.equ XRAMEND =$25F\r
+.equ E2END =$1FF\r
+.equ FLASHEND=$FFF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ;Timer2 compare match Vector Address\r
+.equ OVF2addr=$004 ;Timer2 overflow Vector Address\r
+.equ ICP1addr=$005 ;Timer1 Input Capture Vector Address\r
+.equ OC1Aaddr=$006 ;Timer1 Output Compare A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ;Timer1 Output Compare B Interrupt Vector Address\r
+.equ OVF1addr=$008 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00A ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$00B ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00C ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00D ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00E ;ADC Conversion Complete Interrupt Vector Address\r
+.equ ERDYaddr=$00F ;EEPROM Write Complete Interrupt Vector Address\r
+.equ ACIaddr =$010 ;Analog Comparator Interrupt Vector Address\r
--- /dev/null
+;****************************************************************************************\r
+;* This can be included in the assembly file\r
+;* in order to use the names in the spec sheet.\r
+;* \r
+;* I/O Register Definitions per AT86RF401 spec\r
+;****************************************************************************************\r
+\r
+;***** device directive, will make the assembler check for illegal instructions.\r
+.device AT86RF401\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3F ; Status \r
+.equ SPH =$3E ; Stack Pointer High \r
+.equ SPL =$3D ; Stack Pointer Low \r
+.equ BL_CONFIG =$35 ; Battery Low Configuration \r
+.equ B_DET =$34 ; Button Detect \r
+.equ PWR_CTL =$33 ; Power Control \r
+.equ IO_DATIN =$32 ; I/O Data In \r
+.equ IO_DATOUT =$31 ; I/O Data Out \r
+.equ IO_ENAB =$30 ; I/O Enable\r
+.equ WDTCR =$22 ; Watchdog Timer Control\r
+.equ BTCR =$21 ; Bit Timer Control\r
+.equ BTCNT =$20 ; Bit Timer Count\r
+.equ DEEAR =$1E ; Data EEPROM Address\r
+.equ DEEDR =$1D ; Data EEPROM Data\r
+.equ DEECR =$1C ; Data EEPROM Control\r
+.equ LOCKDET2 =$17 ; Lock Detector Configuration Register 2\r
+.equ VCOTUNE =$16 ; VCO Tuning Register\r
+.equ PWR_ATTEN =$14 ; Power Attenuation Control Register\r
+.equ TX_CNTL =$12 ; Transmitter Control Register\r
+.equ LOCKDET1 =$10 ; Lock Detector Configuration Register 1\r
+.equ SRAM_START =$0060 ; Start of RAM\r
+.equ SRAM_END =$00DF ; End of RAM\r
+\r
+;**** Bit Definitions\r
+; SREG\r
+.equ I =7\r
+.equ T =6\r
+.equ H =5\r
+.equ S =4\r
+.equ V =3\r
+.equ N =2\r
+.equ Z =1\r
+.equ C =0\r
+\r
+; BL_CONFIG\r
+.equ BL =7\r
+.equ BLV =6\r
+.equ BL5 =5\r
+.equ BL4 =4\r
+.equ BL3 =3\r
+.equ BL2 =2\r
+.equ BL1 =1\r
+.equ BL0 =0\r
+\r
+; B_DET\r
+.equ BD5 =5\r
+.equ BD4 =4\r
+.equ BD3 =3\r
+.equ BD2 =2\r
+.equ BD1 =1\r
+.equ BD0 =0\r
+\r
+; PWR_CTL\r
+.equ ACS2 =7\r
+.equ ACS1 =6\r
+.equ ACS0 =5\r
+.equ TM =4\r
+.equ BD =3\r
+.equ BLI =2\r
+.equ SLEEP =1\r
+.equ BBM =0\r
+\r
+; IO_DATIN\r
+.equ IOI5 =5\r
+.equ IOI4 =4\r
+.equ IOI3 =3\r
+.equ IOI2 =2\r
+.equ IOI1 =1\r
+.equ IOI0 =0\r
+\r
+; IO_DATOUT\r
+.equ IOO5 =5\r
+.equ IOO4 =4\r
+.equ IOO3 =3\r
+.equ IOO2 =2\r
+.equ IOO1 =1\r
+.equ IOO0 =0\r
+\r
+; IO_ENAB\r
+.equ BOHYST =6\r
+.equ IOE5 =5\r
+.equ IOE4 =4\r
+.equ IOE3 =3\r
+.equ IOE2 =2\r
+.equ IOE1 =1\r
+.equ IOE0 =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; BTCR\r
+.equ C9 =7\r
+.equ C8 =6\r
+.equ M1 =5\r
+.equ M0 =4\r
+.equ IE =3\r
+.equ F2 =2\r
+.equ DATA =1\r
+.equ F0 =0\r
+\r
+; BTCNT\r
+.equ C7 =7\r
+.equ C6 =6\r
+.equ C5 =5\r
+.equ C4 =4\r
+.equ C3 =3\r
+.equ C2 =2\r
+.equ C1 =1\r
+.equ C0 =0\r
+\r
+; DEEAR\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+; DEEDR\r
+.equ ED7 =7\r
+.equ ED6 =6\r
+.equ ED5 =5\r
+.equ ED4 =4\r
+.equ ED3 =3\r
+.equ ED2 =2\r
+.equ ED1 =1\r
+.equ ED0 =0\r
+\r
+; DEECR\r
+.equ BSY =3\r
+.equ EEU =2\r
+.equ EEL =1\r
+.equ EER =0\r
+\r
+; LOCKDET2\r
+.equ EUD =7\r
+.equ LAT =6\r
+.equ ULC2 =5\r
+.equ ULC1 =4\r
+.equ ULC0 =3\r
+.equ LC2 =2\r
+.equ LC1 =1\r
+.equ LC0 =0\r
+\r
+; VCOTUNE\r
+.equ VCOVDET1 =7\r
+.equ VCOVDET0 =6\r
+.equ VCOTUNE4 =4\r
+.equ VCOTUNE3 =3\r
+.equ VCOTUNE2 =2\r
+.equ VCOTUNE1 =1\r
+.equ VCOTUNE0 =0\r
+\r
+; PWR_ATTEN\r
+.equ PCC2 =5\r
+.equ PCC1 =4\r
+.equ PCC0 =3\r
+.equ PCF2 =2\r
+.equ PCF1 =1\r
+.equ PCF0 =0\r
+\r
+; TX_CNTL\r
+.equ FSK =6\r
+.equ TXE =5\r
+.equ TXK =4\r
+.equ LOC =2\r
+\r
+; LOCKDET1\r
+.equ UPOK =4\r
+.equ ENKO =3\r
+.equ BOD =2\r
+.equ CS1 =1\r
+.equ CS0 =0\r
+\r
+;****************************************************************************************\r
+;* Define global registers\r
+;****************************************************************************************\r
+\r
+.def XL =R26 \r
+.def XH =R27 \r
+.def YL =R28 \r
+.def YH =R29 \r
+.def ZL =R30 \r
+.def ZH =R31 \r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m103def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega103\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :ATmega103\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega103\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ XDIV =$3c\r
+.equ RAMPZ =$3b\r
+.equ EICR =$3a\r
+.equ EIMSK =$39\r
+.equ EIFR =$38\r
+.equ TIMSK =$37\r
+.equ TIFR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OCR0 =$31\r
+.equ ASSR0 =$30\r
+\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ WDTCR =$21\r
+\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ USR =$0b\r
+.equ UCR =$0a\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ PORTE =$03\r
+.equ DDRE =$02\r
+.equ PINE =$01\r
+.equ PINF =$00\r
+\r
+;***** Bit Definitions\r
+\r
+.equ RAMPZ0 =0\r
+\r
+.equ SRE =7\r
+.equ SRW =6\r
+.equ SE =5\r
+.equ SM1 =4\r
+.equ SM0 =3\r
+\r
+.equ XDIVEN =7\r
+.equ XDIV6 =6\r
+.equ XDIV5 =5\r
+.equ XDIV4 =4\r
+.equ XDIV3 =3\r
+.equ XDIV2 =2\r
+.equ XDIV1 =1\r
+.equ XDIV0 =0\r
+\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT7 =7\r
+.equ INT6 =6\r
+.equ INT5 =5\r
+.equ INT4 =4\r
+.equ INT3 =3\r
+.equ INT2 =2\r
+.equ INT1 =1\r
+.equ INT0 =0\r
+\r
+.equ INTF7 =7\r
+.equ INTF6 =6\r
+.equ INTF5 =5\r
+.equ INTF4 =4\r
+\r
+.equ ISC71 =7\r
+.equ ISC70 =6\r
+.equ ISC61 =5\r
+.equ ISC60 =4\r
+.equ ISC51 =3\r
+.equ ISC50 =2\r
+.equ ISC41 =1\r
+.equ ISC40 =0\r
+\r
+.equ OCIE2 =7\r
+.equ TOIE2 =6\r
+.equ TICIE1 =5\r
+.equ OCIE1A =4\r
+.equ OCIE1B =3\r
+.equ TOIE1 =2\r
+.equ OCIE0 =1\r
+.equ TOIE0 =0\r
+\r
+.equ OCF2 =7\r
+.equ TOV2 =6\r
+.equ ICF1 =5\r
+.equ OCF1A =4\r
+.equ OCF1B =3\r
+.equ TOV1 =2\r
+.equ OCF0 =1\r
+.equ TOV0 =0\r
+\r
+.equ PWM0 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+.equ AS0 =3\r
+.equ TCN0UB =2\r
+.equ OCR0UB =1\r
+.equ TCR0UB =0\r
+\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+.equ PE7 =7\r
+.equ PE6 =6\r
+.equ PE5 =5\r
+.equ PE4 =4\r
+.equ PE3 =3\r
+.equ PE2 =2\r
+.equ PE1 =1\r
+.equ PE0 =0\r
+\r
+.equ DDE7 =7\r
+.equ DDE6 =6\r
+.equ DDE5 =5\r
+.equ DDE4 =4\r
+.equ DDE3 =3\r
+.equ DDE2 =2\r
+.equ DDE1 =1\r
+.equ DDE0 =0\r
+\r
+.equ PINE7 =7\r
+.equ PINE6 =6\r
+.equ PINE5 =5\r
+.equ PINE4 =4\r
+.equ PINE3 =3\r
+.equ PINE2 =2\r
+.equ PINE1 =1\r
+.equ PINE0 =0\r
+\r
+.Equ PINF7 =7\r
+.Equ PINF6 =6\r
+.Equ PINF5 =5\r
+.Equ PINF4 =4\r
+.Equ PINF3 =3\r
+.Equ PINF2 =2\r
+.Equ PINF1 =1\r
+.Equ PINF0 =0\r
+\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$0FFF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$FFFF\r
+.equ E2END =$0FFF\r
+.equ FLASHEND=$FFFF\r
+\r
+.equ INT0addr=$002 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$004 ;External Interrupt1 Vector Address\r
+.equ INT2addr=$006 ;External Interrupt2 Vector Address\r
+.equ INT3addr=$008 ;External Interrupt3 Vector Address\r
+.equ INT4addr=$00a ;External Interrupt4 Vector Address\r
+.equ INT5addr=$00c ;External Interrupt5 Vector Address\r
+.equ INT6addr=$00e ;External Interrupt6 Vector Address\r
+.equ INT7addr=$010 ;External Interrupt7 Vector Address\r
+.equ OC2addr =$012 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$014 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$016 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$018 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$01a ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$01c ;Overflow1 Interrupt Vector Address\r
+.equ OC0addr =$01e ;Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr=$020 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$022 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$024 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$026 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$028 ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$02a ;ADC Conversion Complete Handle\r
+.equ EEWRaddr=$02c ;EEPROM Write Complete Handle\r
+.equ ACIaddr =$02e ;Analog Comparator Interrupt Vector Address\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m104def.inc"\r
+;* Title : Register/Bit Definitions for the ATmega104\r
+;* Date : January 25th, 2000\r
+;* Version : 1.0\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail : support@atmel.no\r
+;* Target MCU : ATmega104\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+;$Author: hackbard $\r
+;$Date: 2003-12-06 01:15:10 $\r
+;$Revision: 1.1 $\r
+;$Source: /chroot/cvs/my-code/atmel/include/m104def.inc,v $\r
+\r
+;**** Specify Device ****\r
+;.device ATmega104\r
+\r
+\r
+;*****************************************************************************\r
+; I/O Register Definitions\r
+;*****************************************************************************\r
+\r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+.equ UCSR1C = $9D\r
+.equ UDR1 = $9C\r
+.equ UCSR1A = $9B\r
+.equ UCSR1B = $9A\r
+.equ UBRR1L = $99\r
+.equ UBRR1H = $98\r
+ \r
+.equ UCSR0C = $95\r
+ \r
+.equ UBRR0H = $90\r
+\r
+.equ TCCR3C = $8C\r
+.equ TCCR3A = $8B\r
+.equ TCCR3B = $8A\r
+.equ TCNT3H = $89\r
+.equ TCNT3L = $88\r
+.equ OCR3AH = $87\r
+.equ OCR3AL = $86\r
+.equ OCR3BH = $85\r
+.equ OCR3BL = $84\r
+.equ OCR3CH = $83\r
+.equ OCR3CL = $82\r
+.equ ICR3H = $81\r
+.equ ICR3L = $80\r
+\r
+.equ ETIMSK = $7D\r
+.equ ETIFR = $7C\r
+\r
+.equ TCCR1C = $7A\r
+.equ OCR1CH = $79\r
+.equ OCR1CL = $78\r
+\r
+.equ TWCR = $74\r
+.equ TWDR = $73\r
+.equ TWAR = $72\r
+.equ TWSR = $71\r
+.equ TWBR = $70\r
+ \r
+.equ OSCCAL = $6F\r
+\r
+.equ XMCRA = $6D\r
+.equ XMCRB = $6C\r
+\r
+.equ EICRA = $6A\r
+\r
+.equ SPMCSR = $68\r
+.equ SPMCR = $68 ; old name for SPMCSR\r
+\r
+.equ PORTG = $65\r
+.equ DDRG = $64\r
+.equ PING = $63\r
+\r
+.equ PORTF = $62\r
+.equ DDRF = $61\r
+\r
+;**** I/O Register Definitions ($3F-$00) ****\r
+.equ SREG = $3F\r
+.equ SPH = $3E\r
+.equ SPL = $3D\r
+.equ XDIV = $3C\r
+.equ RAMPZ = $3B\r
+.equ EICRB = $3A\r
+.equ EIMSK = $39\r
+.equ GIMSK = $39 ; old name for EIMSK\r
+.equ GICR = $39 ; old name for EIMSK\r
+.equ EIFR = $38\r
+.equ GIFR = $38 ; old name for EIFR\r
+.equ TIMSK = $37\r
+.equ TIFR = $36\r
+.equ MCUCR = $35\r
+.equ MCUCSR = $34\r
+.equ TCCR0 = $33\r
+.equ TCNT0 = $32\r
+.equ OCR0 = $31\r
+.equ ASSR = $30\r
+.equ TCCR1A = $2F\r
+.equ TCCR1B = $2E\r
+.equ TCNT1H = $2D\r
+.equ TCNT1L = $2C\r
+.equ OCR1AH = $2B\r
+.equ OCR1AL = $2A\r
+.equ OCR1BH = $29\r
+.equ OCR1BL = $28\r
+.equ ICR1H = $27\r
+.equ ICR1L = $26\r
+.equ TCCR2 = $25\r
+.equ TCNT2 = $24\r
+.equ OCR2 = $23\r
+.equ OCDR = $22 ; New\r
+.equ WDTCR = $21\r
+.equ SFIOR = $20 ; New\r
+.equ EEARH = $1F\r
+.equ EEARL = $1E\r
+.equ EEDR = $1D\r
+.equ EECR = $1C\r
+.equ PORTA = $1B\r
+.equ DDRA = $1A\r
+.equ PINA = $19\r
+.equ PORTB = $18\r
+.equ DDRB = $17\r
+.equ PINB = $16\r
+.equ PORTC = $15\r
+.equ DDRC = $14 ; New\r
+.equ PINC = $13 ; New\r
+.equ PORTD = $12\r
+.equ DDRD = $11\r
+.equ PIND = $10\r
+.equ SPDR = $0F\r
+.equ SPSR = $0E\r
+.equ SPCR = $0D\r
+.equ UDR0 = $0C\r
+.equ UCSR0A = $0B\r
+.equ UCSR0B = $0A\r
+.equ UBRR0L = $09\r
+.equ ACSR = $08\r
+.equ ADMUX = $07\r
+.equ ADCSR = $06\r
+.equ ADCH = $05\r
+.equ ADCL = $04\r
+.equ PORTE = $03\r
+.equ DDRE = $02\r
+.equ PINE = $01\r
+.equ PINF = $00\r
+\r
+\r
+;*****************************************************************************\r
+; Bit Definitions\r
+;*****************************************************************************\r
+\r
+;**** MCU Control ****\r
+.equ SRE = 7 ; MCUCR\r
+.equ SRW10 = 6\r
+.equ SE = 5\r
+.equ SM1 = 4\r
+.equ SM0 = 3\r
+.equ SM2 = 2\r
+.equ IVSEL = 1\r
+.equ IVCE = 0\r
+\r
+.equ JTD = 7 ; MCUCSR\r
+.equ JTRF = 4 \r
+.equ WDRF = 3\r
+.equ BORF = 2\r
+.equ EXTRF = 1\r
+.equ PORF = 0\r
+\r
+.equ SRL2 =6 ; XMCRA\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+\r
+.equ XMBK = 7 ; XMCRB\r
+.equ XMM2 = 2\r
+.equ XMM1 = 1\r
+.equ XMM0 = 0\r
+\r
+.equ SPMIE =7 ; SPMCSR\r
+.equ ASB =6 ; backwards compatiblity\r
+.equ ASRE =4 ; backwards compatiblity\r
+.equ RWWSB =6\r
+.equ RWWSRE =4 \r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+.equ IDRD = 7 ; OCDR\r
+.equ OCDR6 = 6\r
+.equ OCDR5 = 5\r
+.equ OCDR4 = 4 \r
+.equ OCDR3 = 3\r
+.equ OCDR2 = 2\r
+.equ OCDR1 = 1\r
+.equ OCDR0 = 0\r
+\r
+.equ XDIVEN = 7 ; XDIV\r
+.equ XDIV6 = 6\r
+.equ XDIV5 = 5\r
+.equ XDIV4 = 4\r
+.equ XDIV3 = 3\r
+.equ XDIV2 = 2\r
+.equ XDIV1 = 1\r
+.equ XDIV0 = 0\r
+\r
+.equ TSM = 7 ; SFIOR\r
+.equ ADHSM = 4\r
+.equ ACME = 3\r
+.equ PUD = 2\r
+.equ PSR0 = 1\r
+.equ PSR1 = 0\r
+.equ PSR2 = 0\r
+.equ PSR3 = 0\r
+.equ PSR321 = 0 \r
+\r
+;**** Analog to Digital Converter ****\r
+.equ ADEN = 7 ; ADCSR\r
+.equ ADSC = 6\r
+.equ ADFR = 5\r
+.equ ADIF = 4\r
+.equ ADIE = 3\r
+.equ ADPS2 = 2\r
+.equ ADPS1 = 1\r
+.equ ADPS0 = 0\r
+\r
+.equ REFS1 =7 ; ADMUX\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;**** Analog Comparator ****\r
+.equ ACD = 7 ; ACSR\r
+.equ ACBG = 6\r
+.equ ACO = 5\r
+.equ ACI = 4\r
+.equ ACIE = 3\r
+.equ ACIC = 2\r
+.equ ACIS1 = 1\r
+.equ ACIS0 = 0\r
+ \r
+\r
+;**** External Interrupts ****\r
+.equ INT7 = 7 ; EIMSK\r
+.equ INT6 = 6\r
+.equ INT5 = 5\r
+.equ INT4 = 4\r
+.equ INT3 = 3\r
+.equ INT2 = 2\r
+.equ INT1 = 1\r
+.equ INT0 = 0\r
+\r
+.equ INTF7 = 7 ; EIFR\r
+.equ INTF6 = 6\r
+.equ INTF5 = 5\r
+.equ INTF4 = 4\r
+.equ INTF3 = 3\r
+.equ INTF2 = 2\r
+.equ INTF1 = 1\r
+.equ INTF0 = 0\r
+\r
+.equ ISC71 = 7 ; EICRB\r
+.equ ISC70 = 6\r
+.equ ISC61 = 5\r
+.equ ISC60 = 4\r
+.equ ISC51 = 3\r
+.equ ISC50 = 2\r
+.equ ISC41 = 1\r
+.equ ISC40 = 0\r
+\r
+.equ ISC31 = 7 ; EICRA\r
+.equ ISC30 = 6\r
+.equ ISC21 = 5\r
+.equ ISC20 = 4\r
+.equ ISC11 = 3\r
+.equ ISC10 = 2\r
+.equ ISC01 = 1\r
+.equ ISC00 = 0\r
+\r
+;**** Timer Interrupts ****\r
+.equ OCIE2 = 7 ; TIMSK\r
+.equ TOIE2 = 6\r
+.equ TICIE1 = 5\r
+.equ OCIE1A = 4\r
+.equ OCIE1B = 3\r
+.equ TOIE1 = 2\r
+.equ OCIE0 = 1\r
+.equ TOIE0 = 0\r
+\r
+.equ TICIE3 = 5 ; ETIMSK\r
+.equ OCIE3A = 4\r
+.equ OCIE3B = 3\r
+.equ TOIE3 = 2\r
+.equ OCIE3C = 1\r
+.equ OCIE1C = 0\r
+\r
+.equ OCF2 = 7 ; TIFR\r
+.equ TOV2 = 6\r
+.equ ICF1 = 5\r
+.equ OCF1A = 4\r
+.equ OCF1B = 3\r
+.equ TOV1 = 2\r
+.equ OCF0 = 1\r
+.equ TOV0 = 0\r
+\r
+.equ ICF3 = 5 ; ETIFR\r
+.equ OCF3A = 4\r
+.equ OCF3B = 3\r
+.equ TOV3 = 2\r
+.equ OCF3C = 1\r
+.equ OCF1C = 0\r
+\r
+;**** Asynchronous Timer ****\r
+.equ AS0 = 3 ; ASSR\r
+.equ TCN0UB = 2\r
+.equ OCR0UB = 1\r
+.equ TCR0UB = 0\r
+\r
+;**** Timer 0 ****\r
+.equ FOC0 = 7 ; TCCR0\r
+.equ PWM0 = 6\r
+.equ COM01 = 5\r
+.equ COM00 = 4\r
+.equ CTC0 = 3\r
+.equ CS02 = 2\r
+.equ CS01 = 1\r
+.equ CS00 = 0\r
+\r
+;**** Timer 1 ****\r
+.equ COM1A1 = 7 ; TCCR1A\r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ COM1C1 = 3\r
+.equ COM1C0 = 2\r
+.equ PWM11 = 1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 = 0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+.equ ICNC1 = 7 ; TCCR1B\r
+.equ ICES1 = 6\r
+.equ CTC11 = 4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 = 3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+.equ FOC1A = 7 ; TCCR1C\r
+.equ FOC1B = 6\r
+.equ FOC1C = 5\r
+\r
+;**** Timer 2 ****\r
+.equ FOC2 = 7 ; TCCR2\r
+.equ PWM2 = 6\r
+.equ COM21 = 5\r
+.equ COM20 = 4\r
+.equ CTC2 = 3\r
+.equ CS22 = 2\r
+.equ CS21 = 1\r
+.equ CS20 = 0\r
+\r
+;**** Timer 3 ****\r
+.equ COM3A1 = 7 ; TCCR3A\r
+.equ COM3A0 = 6\r
+.equ COM3B1 = 5\r
+.equ COM3B0 = 4\r
+.equ COM3C1 = 3\r
+.equ COM3C0 = 2\r
+.equ PWM31 = 1 ; OBSOLETE! Use WGM31\r
+.equ PWM30 = 0 ; OBSOLETE! Use WGM30\r
+.equ WGM31 = 1\r
+.equ WGM30 = 0\r
+\r
+.equ ICNC3 = 7 ; TCCR3B\r
+.equ ICES3 = 6\r
+.equ CTC31 = 4 ; OBSOLETE! Use WGM33\r
+.equ CTC30 = 3 ; OBSOLETE! Use WGM32\r
+.equ WGM33 = 4\r
+.equ WGM32 = 3\r
+.equ CS32 = 2\r
+.equ CS31 = 1\r
+.equ CS30 = 0\r
+\r
+.equ FOC3A = 7 ; TCCR3C\r
+.equ FOC3B = 6\r
+.equ FOC3C = 5\r
+\r
+;**** Watchdog Timer ****\r
+.equ WDCE = 4 ; WDTCR\r
+.equ WDTOE = 4 ; For Mega103 compability\r
+.equ WDE = 3\r
+.equ WDP2 = 2\r
+.equ WDP1 = 1\r
+.equ WDP0 = 0\r
+\r
+;**** EEPROM Control Register ****\r
+.equ EERIE = 3 ; EECR\r
+.equ EEMWE = 2\r
+.equ EEWE = 1\r
+.equ EERE = 0\r
+\r
+;**** USART 0 and USART 1 ****\r
+.equ RXC = 7 ; (UCSRA0/1)\r
+.equ TXC = 6\r
+.equ UDRE = 5\r
+.equ FE = 4\r
+.equ DOR = 3\r
+.equ PE = 2 ; OBSOLETED!\r
+.equ U2X = 1\r
+.equ MPCM = 0\r
+\r
+.equ RXC0 = 7 ; (UCSR0A)\r
+.equ TXC0 = 6\r
+.equ UDRE0 = 5\r
+.equ FE0 = 4\r
+.equ DOR0 = 3\r
+.equ UPE0 = 2\r
+.equ U2X0 = 1\r
+.equ MPCM0 = 0\r
+\r
+.equ RXC1 = 7 ; (UCSR1A)\r
+.equ TXC1 = 6\r
+.equ UDRE1 = 5\r
+.equ FE1 = 4\r
+.equ DOR1 = 3\r
+.equ UPE1 = 2\r
+.equ U2X1 = 1\r
+.equ MPCM1 = 0\r
+\r
+.equ RXCIE = 7 ; (UCSRB0/1)\r
+.equ TXCIE = 6\r
+.equ UDRIE = 5\r
+.equ RXEN = 4\r
+.equ TXEN = 3\r
+.equ UCSZ2 = 2\r
+.equ RXB8 = 1\r
+.equ TXB8 = 0\r
+\r
+.equ RXCIE0 = 7 ; (UCSR0B)\r
+.equ TXCIE0 = 6\r
+.equ UDRIE0 = 5\r
+.equ RXEN0 = 4\r
+.equ TXEN0 = 3\r
+.equ UCSZ02 = 2\r
+.equ RXB80 = 1\r
+.equ TXB80 = 0\r
+\r
+.equ RXCIE1 = 7 ; (UCSR1B)\r
+.equ TXCIE1 = 6\r
+.equ UDRIE1 = 5\r
+.equ RXEN1 = 4\r
+.equ TXEN1 = 3\r
+.equ UCSZ12 = 2\r
+.equ RXB81 = 1\r
+.equ TXB81 = 0\r
+\r
+.equ UMSEL = 6 ; (UCSRC0/1)\r
+.equ UPM1 = 5\r
+.equ UPM0 = 4\r
+.equ USBS = 3\r
+.equ UCSZ1 = 2\r
+.equ UCSZ0 = 1\r
+.equ UCPOL = 0\r
+\r
+.equ UMSEL0 = 6 ; (UCSR0C)\r
+.equ UPM01 = 5\r
+.equ UPM00 = 4\r
+.equ USBS0 = 3\r
+.equ UCSZ01 = 2\r
+.equ UCSZ00 = 1\r
+.equ UCPOL0 = 0\r
+\r
+.equ UMSEL1 = 6 ; (UCSR1C)\r
+.equ UPM11 = 5\r
+.equ UPM10 = 4\r
+.equ USBS1 = 3\r
+.equ UCSZ11 = 2\r
+.equ UCSZ10 = 1\r
+.equ UCPOL1 = 0\r
+\r
+ \r
+;**** SPI ****\r
+.equ SPIE = 7 ; SPCR\r
+.equ SPE = 6\r
+.equ DORD = 5\r
+.equ MSTR = 4\r
+.equ CPOL = 3\r
+.equ CPHA = 2\r
+.equ SPR1 = 1\r
+.equ SPR0 = 0\r
+\r
+.equ SPIF = 7 ; SPSR\r
+.equ WCOL = 6\r
+.equ SPI2X = 0\r
+\r
+;**** TWI ****\r
+ \r
+.equ TWINT = 7\r
+.equ TWEA = 6\r
+.equ TWSTA = 5\r
+.equ TWSTO = 4\r
+.equ TWWC = 3\r
+.equ TWEN = 2\r
+.equ TWIE = 0\r
+.equ TWS7 = 7 ; TWSR\r
+.equ TWS6 = 6\r
+.equ TWS5 = 5\r
+.equ TWS4 = 4\r
+.equ TWS3 = 3\r
+.equ TWGCE = 0 ; TWAR\r
+\r
+ \r
+;**** PORT A ****\r
+.equ PA7 = 7 ; PORTA\r
+.equ PA6 = 6\r
+.equ PA5 = 5\r
+.equ PA4 = 4\r
+.equ PA3 = 3\r
+.equ PA2 = 2\r
+.equ PA1 = 1\r
+.equ PA0 = 0\r
+.equ PORTA7 = 7\r
+.equ PORTA6 = 6\r
+.equ PORTA5 = 5\r
+.equ PORTA4 = 4\r
+.equ PORTA3 = 3\r
+.equ PORTA2 = 2\r
+.equ PORTA1 = 1\r
+.equ PORTA0 = 0\r
+\r
+.equ DDA7 = 7 ; DDRA\r
+.equ DDA6 = 6\r
+.equ DDA5 = 5\r
+.equ DDA4 = 4\r
+.equ DDA3 = 3\r
+.equ DDA2 = 2\r
+.equ DDA1 = 1\r
+.equ DDA0 = 0\r
+\r
+.equ PINA7 = 7 ; PINA\r
+.equ PINA6 = 6\r
+.equ PINA5 = 5\r
+.equ PINA4 = 4\r
+.equ PINA3 = 3\r
+.equ PINA2 = 2\r
+.equ PINA1 = 1\r
+.equ PINA0 = 0\r
+\r
+;**** PORT B ****\r
+.equ PB7 = 7 ; PORTB\r
+.equ PB6 = 6\r
+.equ PB5 = 5\r
+.equ PB4 = 4\r
+.equ PB3 = 3\r
+.equ PB2 = 2\r
+.equ PB1 = 1\r
+.equ PB0 = 0\r
+.equ PORTB7 = 7\r
+.equ PORTB6 = 6\r
+.equ PORTB5 = 5\r
+.equ PORTB4 = 4\r
+.equ PORTB3 = 3\r
+.equ PORTB2 = 2\r
+.equ PORTB1 = 1\r
+.equ PORTB0 = 0\r
+\r
+.equ DDB7 = 7 ; DDRB\r
+.equ DDB6 = 6\r
+.equ DDB5 = 5\r
+.equ DDB4 = 4\r
+.equ DDB3 = 3\r
+.equ DDB2 = 2\r
+.equ DDB1 = 1\r
+.equ DDB0 = 0\r
+\r
+.equ PINB7 = 7 ; PINB\r
+.equ PINB6 = 6\r
+.equ PINB5 = 5\r
+.equ PINB4 = 4\r
+.equ PINB3 = 3\r
+.equ PINB2 = 2\r
+.equ PINB1 = 1\r
+.equ PINB0 = 0\r
+\r
+;**** PORT C ****\r
+.equ PC7 = 7 ; PORTC\r
+.equ PC6 = 6\r
+.equ PC5 = 5\r
+.equ PC4 = 4\r
+.equ PC3 = 3\r
+.equ PC2 = 2\r
+.equ PC1 = 1\r
+.equ PC0 = 0\r
+.equ PORTC7 = 7\r
+.equ PORTC6 = 6\r
+.equ PORTC5 = 5\r
+.equ PORTC4 = 4\r
+.equ PORTC3 = 3\r
+.equ PORTC2 = 2\r
+.equ PORTC1 = 1\r
+.equ PORTC0 = 0\r
+\r
+.equ DDC7 = 7 ; DDRC\r
+.equ DDC6 = 6\r
+.equ DDC5 = 5\r
+.equ DDC4 = 4\r
+.equ DDC3 = 3\r
+.equ DDC2 = 2\r
+.equ DDC1 = 1\r
+.equ DDC0 = 0\r
+\r
+.equ PINC7 = 7 ; PINC\r
+.equ PINC6 = 6\r
+.equ PINC5 = 5\r
+.equ PINC4 = 4\r
+.equ PINC3 = 3\r
+.equ PINC2 = 2\r
+.equ PINC1 = 1\r
+.equ PINC0 = 0\r
+\r
+;**** PORT D ****\r
+.equ PD7 = 7 ; PORTD\r
+.equ PD6 = 6\r
+.equ PD5 = 5\r
+.equ PD4 = 4\r
+.equ PD3 = 3\r
+.equ PD2 = 2\r
+.equ PD1 = 1\r
+.equ PD0 = 0\r
+.equ PORTD7 = 7\r
+.equ PORTD6 = 6\r
+.equ PORTD5 = 5\r
+.equ PORTD4 = 4\r
+.equ PORTD3 = 3\r
+.equ PORTD2 = 2\r
+.equ PORTD1 = 1\r
+.equ PORTD0 = 0\r
+\r
+.equ DDD7 = 7 ; DDRD\r
+.equ DDD6 = 6\r
+.equ DDD5 = 5\r
+.equ DDD4 = 4\r
+.equ DDD3 = 3\r
+.equ DDD2 = 2\r
+.equ DDD1 = 1\r
+.equ DDD0 = 0\r
+\r
+.equ PIND7 = 7 ; PIND\r
+.equ PIND6 = 6\r
+.equ PIND5 = 5\r
+.equ PIND4 = 4\r
+.equ PIND3 = 3\r
+.equ PIND2 = 2\r
+.equ PIND1 = 1\r
+.equ PIND0 = 0\r
+\r
+;**** PORT E ****\r
+.equ PE7 = 7 ; PORTE\r
+.equ PE6 = 6\r
+.equ PE5 = 5\r
+.equ PE4 = 4\r
+.equ PE3 = 3\r
+.equ PE2 = 2\r
+.equ PE1 = 1\r
+.equ PE0 = 0\r
+.equ PORTE7 = 7 ; PORTE\r
+.equ PORTE6 = 6\r
+.equ PORTE5 = 5\r
+.equ PORTE4 = 4\r
+.equ PORTE3 = 3\r
+.equ PORTE2 = 2\r
+.equ PORTE1 = 1\r
+.equ PORTE0 = 0\r
+\r
+.equ DDE7 = 7 ; DDRE\r
+.equ DDE6 = 6\r
+.equ DDE5 = 5\r
+.equ DDE4 = 4\r
+.equ DDE3 = 3\r
+.equ DDE2 = 2\r
+.equ DDE1 = 1\r
+.equ DDE0 = 0\r
+\r
+.equ PINE7 = 7 ; PINE\r
+.equ PINE6 = 6\r
+.equ PINE5 = 5\r
+.equ PINE4 = 4\r
+.equ PINE3 = 3\r
+.equ PINE2 = 2\r
+.equ PINE1 = 1\r
+.equ PINE0 = 0\r
+\r
+;**** PORT F ****\r
+.equ PF7 = 7 ; PORTF\r
+.equ PF6 = 6\r
+.equ PF5 = 5\r
+.equ PF4 = 4\r
+.equ PF3 = 3\r
+.equ PF2 = 2\r
+.equ PF1 = 1\r
+.equ PF0 = 0\r
+.equ PORTF7 = 7\r
+.equ PORTF6 = 6\r
+.equ PORTF5 = 5\r
+.equ PORTF4 = 4\r
+.equ PORTF3 = 3\r
+.equ PORTF2 = 2\r
+.equ PORTF1 = 1\r
+.equ PORTF0 = 0\r
+\r
+.equ DDF7 = 7 ; DDRF\r
+.equ DDF6 = 6\r
+.equ DDF5 = 5\r
+.equ DDF4 = 4\r
+.equ DDF3 = 3\r
+.equ DDF2 = 2\r
+.equ DDF1 = 1\r
+.equ DDF0 = 0\r
+\r
+.equ PINF7 = 7 ; PINF\r
+.equ PINF6 = 6\r
+.equ PINF5 = 5\r
+.equ PINF4 = 4\r
+.equ PINF3 = 3\r
+.equ PINF2 = 2\r
+.equ PINF1 = 1\r
+.equ PINF0 = 0\r
+\r
+;**** PORT G ****\r
+.equ PG4 = 4 ; PORTG\r
+.equ PG3 = 3\r
+.equ PG2 = 2\r
+.equ PG1 = 1\r
+.equ PG0 = 0\r
+\r
+.equ DDG4 = 4 ; DDRG\r
+.equ DDG3 = 3\r
+.equ DDG2 = 2\r
+.equ DDG1 = 1\r
+.equ DDG0 = 0\r
+\r
+.equ PING4 = 4 ; PING\r
+.equ PING3 = 3\r
+.equ PING2 = 2\r
+.equ PING1 = 1\r
+.equ PING0 = 0\r
+\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.\r
+.equ EEPROMEND = $0fff ; Highest EEPROM address.\r
+ \r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $FFFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\/--\ \r
+.equ SMALLBOOTSTART = 0b1111111000000000 ; ($FE00) Smallest boot block is 512W\r
+.equ SECONDBOOTSTART = 0b1111110000000000 ; ($FC00) 2'nd boot block size is 1KW\r
+.equ THIRDBOOTSTART = 0b1111100000000000 ; ($F800) Third boot block size is 2KW\r
+.equ LARGEBOOTSTART = 0b1111000000000000 ; ($F000) Largest boot block is 4KW\r
+\r
+\r
+;**** Page Size ****\r
+.equ PAGESIZE = 128 ; Number of WORDS in a page\r
+\r
+\r
+;**** Interrupt Vectors ****\r
+.equ INT0addr = $002 ; External Interrupt0 Vector Address\r
+.equ INT1addr = $004 ; External Interrupt1 Vector Address\r
+.equ INT2addr = $006 ; External Interrupt2 Vector Address\r
+.equ INT3addr = $008 ; External Interrupt3 Vector Address\r
+.equ INT4addr = $00a ; External Interrupt4 Vector Address\r
+.equ INT5addr = $00c ; External Interrupt5 Vector Address\r
+.equ INT6addr = $00e ; External Interrupt6 Vector Address\r
+.equ INT7addr = $010 ; External Interrupt7 Vector Address\r
+.equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr = $022 ; SPI Interrupt Vector Address\r
+.equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address\r
+.equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address\r
+.equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr = $02a ; ADC Conversion Complete Handle\r
+.equ ERDYaddr = $02c ; EEPROM Write Complete Handle\r
+.equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address\r
+\r
+.equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address\r
+.equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address\r
+.equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address\r
+.equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address\r
+.equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address\r
+.equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address\r
+.equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address\r
+.equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address\r
+.equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address\r
+.equ TWIaddr = $042 ; TWI Interrupt Vector Address\r
+.equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+;**** End of File ****\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m128def.inc"\r
+;* Title : Register/Bit Definitions for the ATmega128\r
+;* Date : 07.09.2001\r
+;* Version : 1.0\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail : avr@atmel.no\r
+;* Target MCU : ATmega128\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;**** Specify Device ****\r
+.device ATmega128\r
+\r
+;*****************************************************************************\r
+; I/O Register Definitions\r
+;*****************************************************************************\r
+\r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+.equ UCSR1C = $9D\r
+.equ UDR1 = $9C\r
+.equ UCSR1A = $9B\r
+.equ UCSR1B = $9A\r
+.equ UBRR1L = $99\r
+.equ UBRR1H = $98\r
+.equ UCSR0C = $95\r
+.equ UBRR0H = $90\r
+.equ TCCR3C = $8C\r
+.equ TCCR3A = $8B\r
+.equ TCCR3B = $8A\r
+.equ TCNT3H = $89\r
+.equ TCNT3L = $88\r
+.equ OCR3AH = $87\r
+.equ OCR3AL = $86\r
+.equ OCR3BH = $85\r
+.equ OCR3BL = $84\r
+.equ OCR3CH = $83\r
+.equ OCR3CL = $82\r
+.equ ICR3H = $81\r
+.equ ICR3L = $80\r
+.equ ETIMSK = $7D\r
+.equ ETIFR = $7C\r
+.equ TCCR1C = $7A\r
+.equ OCR1CH = $79\r
+.equ OCR1CL = $78\r
+.equ TWCR = $74\r
+.equ TWDR = $73\r
+.equ TWAR = $72\r
+.equ TWSR = $71\r
+.equ TWBR = $70\r
+.equ OSCCAL = $6F\r
+.equ XMCRA = $6D\r
+.equ XMCRB = $6C\r
+.equ EICRA = $6A\r
+.equ SPMCSR = $68\r
+.equ SPMCR = $68 ; old name for SPMCSR\r
+.equ PORTG = $65\r
+.equ DDRG = $64\r
+.equ PING = $63\r
+.equ PORTF = $62\r
+.equ DDRF = $61\r
+\r
+;**** I/O Register Definitions ($3F-$00) ****\r
+.equ SREG = $3F\r
+.equ SPH = $3E\r
+.equ SPL = $3D\r
+.equ XDIV = $3C\r
+.equ RAMPZ = $3B\r
+.equ EICRB = $3A\r
+.equ EIMSK = $39\r
+.equ GIMSK = $39 ; old name for EIMSK\r
+.equ GICR = $39 ; old name for EIMSK\r
+.equ EIFR = $38\r
+.equ GIFR = $38 ; old name for EIFR\r
+.equ TIMSK = $37\r
+.equ TIFR = $36\r
+.equ MCUCR = $35\r
+.equ MCUCSR = $34\r
+.equ TCCR0 = $33\r
+.equ TCNT0 = $32\r
+.equ OCR0 = $31\r
+.equ ASSR = $30\r
+.equ TCCR1A = $2F\r
+.equ TCCR1B = $2E\r
+.equ TCNT1H = $2D\r
+.equ TCNT1L = $2C\r
+.equ OCR1AH = $2B\r
+.equ OCR1AL = $2A\r
+.equ OCR1BH = $29\r
+.equ OCR1BL = $28\r
+.equ ICR1H = $27\r
+.equ ICR1L = $26\r
+.equ TCCR2 = $25\r
+.equ TCNT2 = $24\r
+.equ OCR2 = $23\r
+.equ OCDR = $22 ; New\r
+.equ WDTCR = $21\r
+.equ SFIOR = $20 ; New\r
+.equ EEARH = $1F\r
+.equ EEARL = $1E\r
+.equ EEDR = $1D\r
+.equ EECR = $1C\r
+.equ PORTA = $1B\r
+.equ DDRA = $1A\r
+.equ PINA = $19\r
+.equ PORTB = $18\r
+.equ DDRB = $17\r
+.equ PINB = $16\r
+.equ PORTC = $15\r
+.equ DDRC = $14 ; New\r
+.equ PINC = $13 ; New\r
+.equ PORTD = $12\r
+.equ DDRD = $11\r
+.equ PIND = $10\r
+.equ SPDR = $0F\r
+.equ SPSR = $0E\r
+.equ SPCR = $0D\r
+.equ UDR0 = $0C\r
+.equ UCSR0A = $0B\r
+.equ UCSR0B = $0A\r
+.equ UBRR0L = $09\r
+.equ ACSR = $08\r
+.equ ADMUX = $07\r
+.equ ADCSR = $06\r
+.equ ADCH = $05\r
+.equ ADCL = $04\r
+.equ PORTE = $03\r
+.equ DDRE = $02\r
+.equ PINE = $01\r
+.equ PINF = $00\r
+\r
+\r
+;*****************************************************************************\r
+; Bit Definitions\r
+;*****************************************************************************\r
+\r
+;**** MCU Control ****\r
+.equ SRE = 7 ; MCUCR\r
+.equ SRW10 = 6\r
+.equ SE = 5\r
+.equ SM1 = 4\r
+.equ SM0 = 3\r
+.equ SM2 = 2\r
+.equ IVSEL = 1\r
+.equ IVCE = 0\r
+\r
+.equ JTD = 7 ; MCUCSR\r
+.equ JTRF = 4 \r
+.equ WDRF = 3\r
+.equ BORF = 2\r
+.equ EXTRF = 1\r
+.equ PORF = 0\r
+\r
+.equ SRL2 =6 ; XMCRA\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+\r
+.equ XMBK = 7 ; XMCRB\r
+.equ XMM2 = 2\r
+.equ XMM1 = 1\r
+.equ XMM0 = 0\r
+\r
+.equ SPMIE =7 ; SPMCSR\r
+.equ ASB =6 ; backwards compatiblity\r
+.equ ASRE =4 ; backwards compatiblity\r
+.equ RWWSB =6\r
+.equ RWWSRE =4 \r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+.equ IDRD = 7 ; OCDR\r
+.equ OCDR6 = 6\r
+.equ OCDR5 = 5\r
+.equ OCDR4 = 4 \r
+.equ OCDR3 = 3\r
+.equ OCDR2 = 2\r
+.equ OCDR1 = 1\r
+.equ OCDR0 = 0\r
+\r
+.equ XDIVEN = 7 ; XDIV\r
+.equ XDIV6 = 6\r
+.equ XDIV5 = 5\r
+.equ XDIV4 = 4\r
+.equ XDIV3 = 3\r
+.equ XDIV2 = 2\r
+.equ XDIV1 = 1\r
+.equ XDIV0 = 0\r
+\r
+.equ TSM = 7 ; SFIOR\r
+.equ ADHSM = 4\r
+.equ ACME = 3\r
+.equ PUD = 2\r
+.equ PSR0 = 1\r
+.equ PSR1 = 0\r
+.equ PSR2 = 0\r
+.equ PSR3 = 0\r
+.equ PSR321 = 0 \r
+\r
+;**** Analog to Digital Converter ****\r
+.equ ADEN = 7 ; ADCSR\r
+.equ ADSC = 6\r
+.equ ADFR = 5\r
+.equ ADIF = 4\r
+.equ ADIE = 3\r
+.equ ADPS2 = 2\r
+.equ ADPS1 = 1\r
+.equ ADPS0 = 0\r
+\r
+.equ REFS1 =7 ; ADMUX\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;**** Analog Comparator ****\r
+.equ ACD = 7 ; ACSR\r
+.equ ACBG = 6\r
+.equ ACO = 5\r
+.equ ACI = 4\r
+.equ ACIE = 3\r
+.equ ACIC = 2\r
+.equ ACIS1 = 1\r
+.equ ACIS0 = 0\r
+ \r
+\r
+;**** External Interrupts ****\r
+.equ INT7 = 7 ; EIMSK\r
+.equ INT6 = 6\r
+.equ INT5 = 5\r
+.equ INT4 = 4\r
+.equ INT3 = 3\r
+.equ INT2 = 2\r
+.equ INT1 = 1\r
+.equ INT0 = 0\r
+\r
+.equ INTF7 = 7 ; EIFR\r
+.equ INTF6 = 6\r
+.equ INTF5 = 5\r
+.equ INTF4 = 4\r
+.equ INTF3 = 3\r
+.equ INTF2 = 2\r
+.equ INTF1 = 1\r
+.equ INTF0 = 0\r
+\r
+.equ ISC71 = 7 ; EICRB\r
+.equ ISC70 = 6\r
+.equ ISC61 = 5\r
+.equ ISC60 = 4\r
+.equ ISC51 = 3\r
+.equ ISC50 = 2\r
+.equ ISC41 = 1\r
+.equ ISC40 = 0\r
+\r
+.equ ISC31 = 7 ; EICRA\r
+.equ ISC30 = 6\r
+.equ ISC21 = 5\r
+.equ ISC20 = 4\r
+.equ ISC11 = 3\r
+.equ ISC10 = 2\r
+.equ ISC01 = 1\r
+.equ ISC00 = 0\r
+\r
+;**** Timer Interrupts ****\r
+.equ OCIE2 = 7 ; TIMSK\r
+.equ TOIE2 = 6\r
+.equ TICIE1 = 5\r
+.equ OCIE1A = 4\r
+.equ OCIE1B = 3\r
+.equ TOIE1 = 2\r
+.equ OCIE0 = 1\r
+.equ TOIE0 = 0\r
+\r
+.equ TICIE3 = 5 ; ETIMSK\r
+.equ OCIE3A = 4\r
+.equ OCIE3B = 3\r
+.equ TOIE3 = 2\r
+.equ OCIE3C = 1\r
+.equ OCIE1C = 0\r
+\r
+.equ OCF2 = 7 ; TIFR\r
+.equ TOV2 = 6\r
+.equ ICF1 = 5\r
+.equ OCF1A = 4\r
+.equ OCF1B = 3\r
+.equ TOV1 = 2\r
+.equ OCF0 = 1\r
+.equ TOV0 = 0\r
+\r
+.equ ICF3 = 5 ; ETIFR\r
+.equ OCF3A = 4\r
+.equ OCF3B = 3\r
+.equ TOV3 = 2\r
+.equ OCF3C = 1\r
+.equ OCF1C = 0\r
+\r
+;**** Asynchronous Timer ****\r
+.equ AS0 = 3 ; ASSR\r
+.equ TCN0UB = 2\r
+.equ OCR0UB = 1\r
+.equ TCR0UB = 0\r
+\r
+;**** Timer 0 ****\r
+.equ FOC0 = 7 ; TCCR0\r
+.equ WGM00 = 6\r
+.equ COM01 = 5\r
+.equ COM00 = 4\r
+.equ WGM01 = 3\r
+.equ CS02 = 2\r
+.equ CS01 = 1\r
+.equ CS00 = 0\r
+\r
+;**** Timer 1 ****\r
+.equ COM1A1 = 7 ; TCCR1A\r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ COM1C1 = 3\r
+.equ COM1C0 = 2\r
+.equ PWM11 = 1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 = 0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+.equ ICNC1 = 7 ; TCCR1B\r
+.equ ICES1 = 6\r
+.equ CTC11 = 4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 = 3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+.equ FOC1A = 7 ; TCCR1C\r
+.equ FOC1B = 6\r
+.equ FOC1C = 5\r
+\r
+;**** Timer 2 ****\r
+.equ FOC2 = 7 ; TCCR2\r
+.equ WGM20 = 6\r
+.equ COM21 = 5\r
+.equ COM20 = 4\r
+.equ WGM21 = 3\r
+.equ CS22 = 2\r
+.equ CS21 = 1\r
+.equ CS20 = 0\r
+\r
+;**** Timer 3 ****\r
+.equ COM3A1 = 7 ; TCCR3A\r
+.equ COM3A0 = 6\r
+.equ COM3B1 = 5\r
+.equ COM3B0 = 4\r
+.equ COM3C1 = 3\r
+.equ COM3C0 = 2\r
+.equ PWM31 = 1 ; OBSOLETE! Use WGM31\r
+.equ PWM30 = 0 ; OBSOLETE! Use WGM30\r
+.equ WGM31 = 1\r
+.equ WGM30 = 0\r
+\r
+.equ ICNC3 = 7 ; TCCR3B\r
+.equ ICES3 = 6\r
+.equ CTC31 = 4 ; OBSOLETE! Use WGM33\r
+.equ CTC30 = 3 ; OBSOLETE! Use WGM32\r
+.equ WGM33 = 4\r
+.equ WGM32 = 3\r
+.equ CS32 = 2\r
+.equ CS31 = 1\r
+.equ CS30 = 0\r
+\r
+.equ FOC3A = 7 ; TCCR3C\r
+.equ FOC3B = 6\r
+.equ FOC3C = 5\r
+\r
+;**** Watchdog Timer ****\r
+.equ WDCE = 4 ; WDTCR\r
+.equ WDTOE = 4 ; For Mega103 compability\r
+.equ WDE = 3\r
+.equ WDP2 = 2\r
+.equ WDP1 = 1\r
+.equ WDP0 = 0\r
+\r
+;**** EEPROM Control Register ****\r
+.equ EERIE = 3 ; EECR\r
+.equ EEMWE = 2\r
+.equ EEWE = 1\r
+.equ EERE = 0\r
+\r
+;**** USART 0 and USART 1 ****\r
+.equ RXC = 7 ; (UCSRA0/1)\r
+.equ TXC = 6\r
+.equ UDRE = 5\r
+.equ FE = 4\r
+.equ DOR = 3\r
+.equ PE = 2 ; OBSOLETED!\r
+.equ U2X = 1\r
+.equ MPCM = 0\r
+\r
+.equ RXC0 = 7 ; (UCSR0A)\r
+.equ TXC0 = 6\r
+.equ UDRE0 = 5\r
+.equ FE0 = 4\r
+.equ DOR0 = 3\r
+.equ UPE0 = 2\r
+.equ U2X0 = 1\r
+.equ MPCM0 = 0\r
+\r
+.equ RXC1 = 7 ; (UCSR1A)\r
+.equ TXC1 = 6\r
+.equ UDRE1 = 5\r
+.equ FE1 = 4\r
+.equ DOR1 = 3\r
+.equ UPE1 = 2\r
+.equ U2X1 = 1\r
+.equ MPCM1 = 0\r
+\r
+.equ RXCIE = 7 ; (UCSRB0/1)\r
+.equ TXCIE = 6\r
+.equ UDRIE = 5\r
+.equ RXEN = 4\r
+.equ TXEN = 3\r
+.equ UCSZ2 = 2\r
+.equ RXB8 = 1\r
+.equ TXB8 = 0\r
+\r
+.equ RXCIE0 = 7 ; (UCSR0B)\r
+.equ TXCIE0 = 6\r
+.equ UDRIE0 = 5\r
+.equ RXEN0 = 4\r
+.equ TXEN0 = 3\r
+.equ UCSZ02 = 2\r
+.equ RXB80 = 1\r
+.equ TXB80 = 0\r
+\r
+.equ RXCIE1 = 7 ; (UCSR1B)\r
+.equ TXCIE1 = 6\r
+.equ UDRIE1 = 5\r
+.equ RXEN1 = 4\r
+.equ TXEN1 = 3\r
+.equ UCSZ12 = 2\r
+.equ RXB81 = 1\r
+.equ TXB81 = 0\r
+\r
+.equ UMSEL = 6 ; (UCSRC0/1)\r
+.equ UPM1 = 5\r
+.equ UPM0 = 4\r
+.equ USBS = 3\r
+.equ UCSZ1 = 2\r
+.equ UCSZ0 = 1\r
+.equ UCPOL = 0\r
+\r
+.equ UMSEL0 = 6 ; (UCSR0C)\r
+.equ UPM01 = 5\r
+.equ UPM00 = 4\r
+.equ USBS0 = 3\r
+.equ UCSZ01 = 2\r
+.equ UCSZ00 = 1\r
+.equ UCPOL0 = 0\r
+\r
+.equ UMSEL1 = 6 ; (UCSR1C)\r
+.equ UPM11 = 5\r
+.equ UPM10 = 4\r
+.equ USBS1 = 3\r
+.equ UCSZ11 = 2\r
+.equ UCSZ10 = 1\r
+.equ UCPOL1 = 0\r
+\r
+ \r
+;**** SPI ****\r
+.equ SPIE = 7 ; SPCR\r
+.equ SPE = 6\r
+.equ DORD = 5\r
+.equ MSTR = 4\r
+.equ CPOL = 3\r
+.equ CPHA = 2\r
+.equ SPR1 = 1\r
+.equ SPR0 = 0\r
+\r
+.equ SPIF = 7 ; SPSR\r
+.equ WCOL = 6\r
+.equ SPI2X = 0\r
+\r
+;**** TWI **** \r
+.equ TWINT = 7 ;TWCR\r
+.equ TWEA = 6\r
+.equ TWSTA = 5\r
+.equ TWSTO = 4\r
+.equ TWWC = 3\r
+.equ TWEN = 2\r
+.equ TWIE = 0\r
+\r
+.equ TWS7 = 7 ; TWSR\r
+.equ TWS6 = 6\r
+.equ TWS5 = 5\r
+.equ TWS4 = 4\r
+.equ TWS3 = 3\r
+.equ TWPS1 = 1\r
+.equ TWPS0 = 0\r
+\r
+.equ TWA6 = 7\r
+.equ TWA5 = 6\r
+.equ TWA4 = 5\r
+.equ TWA3 = 4\r
+.equ TWA2 = 3\r
+.equ TWA1 = 2\r
+.equ TWA0 = 1\r
+.equ TWGCE = 0 ; TWAR\r
+\r
+ \r
+;**** PORT A ****\r
+.equ PA7 = 7 ; PORTA\r
+.equ PA6 = 6\r
+.equ PA5 = 5\r
+.equ PA4 = 4\r
+.equ PA3 = 3\r
+.equ PA2 = 2\r
+.equ PA1 = 1\r
+.equ PA0 = 0\r
+.equ PORTA7 = 7\r
+.equ PORTA6 = 6\r
+.equ PORTA5 = 5\r
+.equ PORTA4 = 4\r
+.equ PORTA3 = 3\r
+.equ PORTA2 = 2\r
+.equ PORTA1 = 1\r
+.equ PORTA0 = 0\r
+\r
+.equ DDA7 = 7 ; DDRA\r
+.equ DDA6 = 6\r
+.equ DDA5 = 5\r
+.equ DDA4 = 4\r
+.equ DDA3 = 3\r
+.equ DDA2 = 2\r
+.equ DDA1 = 1\r
+.equ DDA0 = 0\r
+\r
+.equ PINA7 = 7 ; PINA\r
+.equ PINA6 = 6\r
+.equ PINA5 = 5\r
+.equ PINA4 = 4\r
+.equ PINA3 = 3\r
+.equ PINA2 = 2\r
+.equ PINA1 = 1\r
+.equ PINA0 = 0\r
+\r
+;**** PORT B ****\r
+.equ PB7 = 7 ; PORTB\r
+.equ PB6 = 6\r
+.equ PB5 = 5\r
+.equ PB4 = 4\r
+.equ PB3 = 3\r
+.equ PB2 = 2\r
+.equ PB1 = 1\r
+.equ PB0 = 0\r
+.equ PORTB7 = 7\r
+.equ PORTB6 = 6\r
+.equ PORTB5 = 5\r
+.equ PORTB4 = 4\r
+.equ PORTB3 = 3\r
+.equ PORTB2 = 2\r
+.equ PORTB1 = 1\r
+.equ PORTB0 = 0\r
+\r
+.equ DDB7 = 7 ; DDRB\r
+.equ DDB6 = 6\r
+.equ DDB5 = 5\r
+.equ DDB4 = 4\r
+.equ DDB3 = 3\r
+.equ DDB2 = 2\r
+.equ DDB1 = 1\r
+.equ DDB0 = 0\r
+\r
+.equ PINB7 = 7 ; PINB\r
+.equ PINB6 = 6\r
+.equ PINB5 = 5\r
+.equ PINB4 = 4\r
+.equ PINB3 = 3\r
+.equ PINB2 = 2\r
+.equ PINB1 = 1\r
+.equ PINB0 = 0\r
+\r
+;**** PORT C ****\r
+.equ PC7 = 7 ; PORTC\r
+.equ PC6 = 6\r
+.equ PC5 = 5\r
+.equ PC4 = 4\r
+.equ PC3 = 3\r
+.equ PC2 = 2\r
+.equ PC1 = 1\r
+.equ PC0 = 0\r
+.equ PORTC7 = 7\r
+.equ PORTC6 = 6\r
+.equ PORTC5 = 5\r
+.equ PORTC4 = 4\r
+.equ PORTC3 = 3\r
+.equ PORTC2 = 2\r
+.equ PORTC1 = 1\r
+.equ PORTC0 = 0\r
+\r
+.equ DDC7 = 7 ; DDRC\r
+.equ DDC6 = 6\r
+.equ DDC5 = 5\r
+.equ DDC4 = 4\r
+.equ DDC3 = 3\r
+.equ DDC2 = 2\r
+.equ DDC1 = 1\r
+.equ DDC0 = 0\r
+\r
+.equ PINC7 = 7 ; PINC\r
+.equ PINC6 = 6\r
+.equ PINC5 = 5\r
+.equ PINC4 = 4\r
+.equ PINC3 = 3\r
+.equ PINC2 = 2\r
+.equ PINC1 = 1\r
+.equ PINC0 = 0\r
+\r
+;**** PORT D ****\r
+.equ PD7 = 7 ; PORTD\r
+.equ PD6 = 6\r
+.equ PD5 = 5\r
+.equ PD4 = 4\r
+.equ PD3 = 3\r
+.equ PD2 = 2\r
+.equ PD1 = 1\r
+.equ PD0 = 0\r
+.equ PORTD7 = 7\r
+.equ PORTD6 = 6\r
+.equ PORTD5 = 5\r
+.equ PORTD4 = 4\r
+.equ PORTD3 = 3\r
+.equ PORTD2 = 2\r
+.equ PORTD1 = 1\r
+.equ PORTD0 = 0\r
+\r
+.equ DDD7 = 7 ; DDRD\r
+.equ DDD6 = 6\r
+.equ DDD5 = 5\r
+.equ DDD4 = 4\r
+.equ DDD3 = 3\r
+.equ DDD2 = 2\r
+.equ DDD1 = 1\r
+.equ DDD0 = 0\r
+\r
+.equ PIND7 = 7 ; PIND\r
+.equ PIND6 = 6\r
+.equ PIND5 = 5\r
+.equ PIND4 = 4\r
+.equ PIND3 = 3\r
+.equ PIND2 = 2\r
+.equ PIND1 = 1\r
+.equ PIND0 = 0\r
+\r
+;**** PORT E ****\r
+.equ PE7 = 7 ; PORTE\r
+.equ PE6 = 6\r
+.equ PE5 = 5\r
+.equ PE4 = 4\r
+.equ PE3 = 3\r
+.equ PE2 = 2\r
+.equ PE1 = 1\r
+.equ PE0 = 0\r
+.equ PORTE7 = 7 ; PORTE\r
+.equ PORTE6 = 6\r
+.equ PORTE5 = 5\r
+.equ PORTE4 = 4\r
+.equ PORTE3 = 3\r
+.equ PORTE2 = 2\r
+.equ PORTE1 = 1\r
+.equ PORTE0 = 0\r
+\r
+.equ DDE7 = 7 ; DDRE\r
+.equ DDE6 = 6\r
+.equ DDE5 = 5\r
+.equ DDE4 = 4\r
+.equ DDE3 = 3\r
+.equ DDE2 = 2\r
+.equ DDE1 = 1\r
+.equ DDE0 = 0\r
+\r
+.equ PINE7 = 7 ; PINE\r
+.equ PINE6 = 6\r
+.equ PINE5 = 5\r
+.equ PINE4 = 4\r
+.equ PINE3 = 3\r
+.equ PINE2 = 2\r
+.equ PINE1 = 1\r
+.equ PINE0 = 0\r
+\r
+;**** PORT F ****\r
+.equ PF7 = 7 ; PORTF\r
+.equ PF6 = 6\r
+.equ PF5 = 5\r
+.equ PF4 = 4\r
+.equ PF3 = 3\r
+.equ PF2 = 2\r
+.equ PF1 = 1\r
+.equ PF0 = 0\r
+.equ PORTF7 = 7\r
+.equ PORTF6 = 6\r
+.equ PORTF5 = 5\r
+.equ PORTF4 = 4\r
+.equ PORTF3 = 3\r
+.equ PORTF2 = 2\r
+.equ PORTF1 = 1\r
+.equ PORTF0 = 0\r
+\r
+.equ DDF7 = 7 ; DDRF\r
+.equ DDF6 = 6\r
+.equ DDF5 = 5\r
+.equ DDF4 = 4\r
+.equ DDF3 = 3\r
+.equ DDF2 = 2\r
+.equ DDF1 = 1\r
+.equ DDF0 = 0\r
+\r
+.equ PINF7 = 7 ; PINF\r
+.equ PINF6 = 6\r
+.equ PINF5 = 5\r
+.equ PINF4 = 4\r
+.equ PINF3 = 3\r
+.equ PINF2 = 2\r
+.equ PINF1 = 1\r
+.equ PINF0 = 0\r
+\r
+;**** PORT G ****\r
+.equ PG4 = 4 ; PORTG\r
+.equ PG3 = 3\r
+.equ PG2 = 2\r
+.equ PG1 = 1\r
+.equ PG0 = 0\r
+\r
+.equ DDG4 = 4 ; DDRG\r
+.equ DDG3 = 3\r
+.equ DDG2 = 2\r
+.equ DDG1 = 1\r
+.equ DDG0 = 0\r
+\r
+.equ PING4 = 4 ; PING\r
+.equ PING3 = 3\r
+.equ PING2 = 2\r
+.equ PING1 = 1\r
+.equ PING0 = 0\r
+\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.\r
+.equ EEPROMEND = $0fff ; Highest EEPROM address.\r
+ \r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $FFFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\/--\ \r
+.equ SMALLBOOTSTART = 0b1111111000000000 ; ($FE00) Smallest boot block is 512W\r
+.equ SECONDBOOTSTART = 0b1111110000000000 ; ($FC00) 2'nd boot block size is 1KW\r
+.equ THIRDBOOTSTART = 0b1111100000000000 ; ($F800) Third boot block size is 2KW\r
+.equ LARGEBOOTSTART = 0b1111000000000000 ; ($F000) Largest boot block is 4KW\r
+\r
+\r
+;**** Page Size ****\r
+.equ PAGESIZE = 128 ; Number of WORDS in a page\r
+\r
+\r
+;**** Interrupt Vectors ****\r
+.equ INT0addr = $002 ; External Interrupt0 Vector Address\r
+.equ INT1addr = $004 ; External Interrupt1 Vector Address\r
+.equ INT2addr = $006 ; External Interrupt2 Vector Address\r
+.equ INT3addr = $008 ; External Interrupt3 Vector Address\r
+.equ INT4addr = $00a ; External Interrupt4 Vector Address\r
+.equ INT5addr = $00c ; External Interrupt5 Vector Address\r
+.equ INT6addr = $00e ; External Interrupt6 Vector Address\r
+.equ INT7addr = $010 ; External Interrupt7 Vector Address\r
+.equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr = $022 ; SPI Interrupt Vector Address\r
+.equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address\r
+.equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address\r
+.equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr = $02a ; ADC Conversion Complete Handle\r
+.equ ERDYaddr = $02c ; EEPROM Write Complete Handle\r
+.equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address\r
+\r
+.equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address\r
+.equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address\r
+.equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address\r
+.equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address\r
+.equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address\r
+.equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address\r
+.equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address\r
+.equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address\r
+.equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address\r
+.equ TWIaddr = $042 ; TWI Interrupt Vector Address\r
+.equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+;**** End of File ****\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m161def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega161\r
+;* Date :00.12.12\r
+;* Version :\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega161\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega161\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ EMCUCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OCR0 =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ TCCR2 =$27\r
+.equ ASSR =$26\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ TCNT2 =$23\r
+.equ OCR2 =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR0 =$0c\r
+.equ UDR =$0c ;for compatibility with s8515\r
+.equ UCSR0A =$0b\r
+.equ USR =$0b ;for compatibility with s8515\r
+.equ UCSR0B =$0a\r
+.equ UCR =$0a ;for compatibility with s8515\r
+.equ UBRR0 =$09\r
+.equ UBRR =$09 ;for compatibility with s8515\r
+.equ ACSR =$08\r
+.equ PORTE =$07\r
+.equ DDRE =$06\r
+.equ PINE =$05\r
+.equ UDR1 =$03\r
+.equ UCSR1A =$02\r
+.equ UCSR1B =$01\r
+.equ UBRR1 =$00\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TOIE2 =4\r
+.equ TICIE1 =3\r
+.equ OCIE2 =2\r
+.equ TOIE0 =1\r
+.equ OCIE0 =0\r
+\r
+;TIFR\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ TOV2 =4\r
+.equ ICF1 =3\r
+.equ OCF2 =2\r
+.equ TOV0 =1\r
+.equ OCF0 =0\r
+\r
+;SPMCR\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;EMCUCR\r
+.equ SM0 =7\r
+.equ SRL2 =6\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+.equ ISC2 =0\r
+\r
+;MCUCR\r
+.equ SRE =7\r
+.equ SRW =6 ;for compatibility with s8515\r
+.equ SRW10 =6\r
+.equ SE =5\r
+.equ SM =4 ;for compatibility with s8515\r
+.equ SM1 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ PWM0 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;SFIOR\r
+.equ PSR10 =0\r
+.equ PSR2 =1\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+;WDTCR\r
+.equ WDDE =4 \r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;PORTE\r
+.equ PE2 =2\r
+.equ PE1 =1\r
+.equ PE0 =0\r
+\r
+;DDRE\r
+.equ DDE2 =2\r
+.equ DDE1 =1\r
+.equ DDE0 =0\r
+\r
+;PINE\r
+.equ PINE2 =2\r
+.equ PINE1 =1\r
+.equ PINE0 =0\r
+\r
+; USR (for compatibility with s8515)\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ U2X =1\r
+\r
+;UCSR0A\r
+.equ RXC0 =7\r
+.equ TXC0 =6\r
+.equ UDRE0 =5\r
+.equ FE0 =4\r
+.equ OR0 =3\r
+.equ U2X0 =1\r
+.equ MPCM0 =0\r
+\r
+;UCSR1A\r
+.equ RXC1 =7\r
+.equ TXC1 =6\r
+.equ UDRE1 =5\r
+.equ FE1 =4\r
+.equ OR1 =3\r
+.equ U2X1 =1\r
+.equ MPCM1 =0\r
+\r
+; SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+; SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+; UCR (for compatibility with s8515)\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+; UCSR0B\r
+.equ RXCIE0 =7\r
+.equ TXCIE0 =6\r
+.equ UDRIE0 =5\r
+.equ RXEN0 =4\r
+.equ TXEN0 =3\r
+.equ CHR90 =2\r
+.equ RXB80 =1\r
+.equ TXB80 =0\r
+\r
+; UCSR1B\r
+.equ RXCIE1 =7\r
+.equ TXCIE1 =6\r
+.equ UDRIE1 =5\r
+.equ RXEN1 =4\r
+.equ TXEN1 =3\r
+.equ CHR91 =2\r
+.equ RXB81 =1\r
+.equ TXB81 =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ AINBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+; Boot loader Lock bit\r
+.equ BLB12 =5\r
+.equ BLB11 =4\r
+.equ BLB02 =3\r
+.equ BLB01 =2\r
+\r
+;X,Y,Z pointer\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND =$1FFF\r
+.equ E2END =$1FF\r
+.equ RAMEND =$45F\r
+.equ XRAMEND =$FFFF\r
+\r
+.equ BOOTSTART =$1E00\r
+\r
+.equ INT0addr =$002 ;External Interrupt0 Vector Address\r
+.equ INT1addr =$004 ;External Interrupt1 Vector Address\r
+.equ INT2addr =$006 ;External Interrupt1 Vector Address\r
+.equ CMP2addr =$008 ;Input Capture1 Interrupt Vector Address\r
+.equ OVF2addr =$00a ;Overflow1 Interrupt Vector Address\r
+.equ ICP1addr =$00c ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr =$00e ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr =$010 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr =$012 ;Overflow1 Interrupt Vector Address\r
+.equ CMP0addr =$014 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr =$016 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$018 ;SPI Interrupt Vector Address\r
+.equ URXC0addr =$01a ;UART Receive Complete Interrupt Vector Address\r
+.equ URXC1addr =$01c ;UART Receive Complete Interrupt Vector Address\r
+.equ UDRE0addr =$01e ;UART Data Register Empty Interrupt Vector Address\r
+.equ UDRE1addr =$020 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXC0addr =$022 ;UART Transmit Complete Interrupt Vector Address\r
+.equ UTXC1addr =$024 ;UART Transmit Complete Interrupt Vector Address\r
+.equ EERDYaddr =$026 ;UART Transmit Complete Interrupt Vector Address\r
+.equ ACIaddr =$028 ;Analog Comparator Interrupt Vector Address\r
+\r
+;for compatibility with s8515\r
+.equ URXCaddr =$01a ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr =$01e ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr =$022 ;UART Transmit Complete Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m162def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega162\r
+;* Date :2001.09.19\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega162\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega162\r
+ \r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+;**** Not available in Mega162 compatibility mode ****\r
+.equ TCCR3A =$8b\r
+.equ TCCR3B =$8a \r
+.equ TCNT3H =$89\r
+.equ TCNT3L =$88\r
+.equ OCR3AH =$87\r
+.equ OCR3AL =$86 \r
+.equ OCR3BH =$85\r
+.equ OCR3BL =$84\r
+.equ ICR3H =$81\r
+.equ ICR3L =$80\r
+.equ ETIMSK =$7d\r
+.equ ETIFR =$7c\r
+.equ PCMSK1 =$6c\r
+.equ PCMSK0 =$6b\r
+.equ CLKPR =$61 \r
+ \r
+;***** I/O Register Definitions \r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ UCSR1C =$3c ; Note! UCSR1C equals UBRR1H\r
+.equ UBRR1H =$3c ; Note! UCSR1C equals UBRR1H\r
+.equ EIMSK =$3b \r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ; new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ EMCUCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further \r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OCR0 =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ TCCR2 =$27\r
+.equ ASSR =$26\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ TCNT2 =$23\r
+.equ OCR2 =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20 ; Old ATmega161\r
+.equ UCSR0C =$20 ; Note! UCSR0C equals UBRR0H\r
+.equ UBRR0H =$20 ; Note! UCSR0C equals UBRR0H \r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR0 =$0c\r
+.equ UDR =$0c ;for compatibility with s8515\r
+.equ UCSR0A =$0b\r
+.equ USR =$0b ;for compatibility with s8515\r
+.equ UCSR0B =$0a\r
+.equ UCR =$0a ;for compatibility with s8515\r
+.equ UBRR0 =$09 ;Old mega161\r
+.equ UBRR0L =$09 \r
+.equ UBRR =$09 ;for compatibility with s8515\r
+.equ ACSR =$08\r
+.equ PORTE =$07\r
+.equ DDRE =$06\r
+.equ PINE =$05\r
+.equ OSCCAL =$04 ; New\r
+.equ UDR1 =$03\r
+.equ UCSR1A =$02\r
+.equ UCSR1B =$01\r
+.equ UBRR1 =$00 ;Old mega161\r
+.equ UBRR1L =$00\r
+\r
+;***** Bit Definitions\r
+;TCCR3A\r
+.equ COM3A1 =7\r
+.equ COM3A0 =6\r
+.equ COM3B1 =5\r
+.equ COM3B0 =4\r
+.equ FOC3A =3\r
+.equ FOC3B =2\r
+.equ WGM31 =1\r
+.equ WGM30 =0\r
+\r
+;TCCR3A\r
+.equ ICNC3 =7\r
+.equ ICES3 =6\r
+.equ WGM33 =4\r
+.equ WGM32 =3\r
+.equ CS32 =2\r
+.equ CS31 =1\r
+.equ CS30 =0\r
+\r
+;ETIMSK\r
+.equ TICIE3 =5\r
+.equ OCIE3A =4\r
+.equ OCIE3B =3\r
+.equ TOIE3 =2\r
+ \r
+;ETIFR\r
+.equ ICF3 =5\r
+.equ OCF3A =4\r
+.equ OCF3B =3\r
+.equ TOV3 =2\r
+\r
+;PCMSK1\r
+.equ PCINT15 =7\r
+.equ PCINT14 =6\r
+.equ PCINT13 =5\r
+.equ PCINT12 =4 \r
+.equ PCINT11 =3\r
+.equ PCINT10 =2 \r
+.equ PCINT9 =1\r
+.equ PCINT8 =0\r
+ \r
+;PCMSK1\r
+.equ PCINT7 =7\r
+.equ PCINT6 =6\r
+.equ PCINT5 =5\r
+.equ PCINT4 =4 \r
+.equ PCINT3 =3\r
+.equ PCINT2 =2 \r
+.equ PCINT1 =1\r
+.equ PCINT0 =0\r
+\r
+;CLKPR\r
+.equ CLKPCE =7\r
+.equ CLKPS3 =3\r
+.equ CLKPS2 =2 \r
+.equ CLKPS1 =1\r
+.equ CLKPS0 =0\r
+ \r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ PCIE1 =4\r
+.equ PCIE0 =3 \r
+.equ IVSEL =1 ; Interrupt vector select\r
+.equ IVCE =0 ; Interrupt vector change enable\r
+ \r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+.equ PCIF1 =4\r
+.equ PCIF0 =3 \r
+ \r
+ \r
+;TIMSK\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ OCIE2 =4\r
+.equ TICIE1 =3\r
+.equ TOIE2 =2\r
+.equ TOIE0 =1\r
+.equ OCIE0 =0\r
+\r
+;TIFR\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ OCF2 =4\r
+.equ ICF1 =3\r
+.equ TOV2 =2\r
+.equ TOV0 =1\r
+.equ OCF0 =0\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ ASB =6 ; old\r
+.equ RWWSRE =4\r
+.equ ASRE =4 ; old\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;EMCUCR\r
+.equ SM0 =7\r
+.equ SRL2 =6\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+.equ ISC2 =0\r
+\r
+;MCUCR\r
+.equ SRE =7\r
+.equ SRW =6 ;for compatibility with s8515\r
+.equ SRW10 =6\r
+.equ SE =5\r
+.equ SM =4 ;for compatibility with s8515\r
+.equ SM1 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUSR\r
+.equ JTD =7 \r
+.equ SM2 =5 \r
+.equ JTRF =4 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ WGM00 =6\r
+.equ PWM0 =6 ; OBSOLETE! Use WGM00\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ WGM01 =3\r
+.equ CTC0 =3 ; OBSOLETE! Use WGM01\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;SFIOR\r
+.equ TSM = 7\r
+.equ XMBK = 6 ; Added for Mega162\r
+.equ XMM2 = 5\r
+.equ XMM1 = 4\r
+.equ XMM0 = 3\r
+.equ PUD = 2\r
+.equ PSR2 = 1\r
+.equ PSR10 = 0 ; Note: The prescaler reset is shared\r
+ ; between timer 0 and 1.\r
+.equ PSR1 = 0\r
+.equ PSR0 = 0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ WGM11 =1\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ WGM13 =4\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM12 =3\r
+.equ CTC1 =3 ; Old Mega161\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ WGM20 =6\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ WGM21 =3\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDCE =4 ; Added for Mega161B\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PORTA7 =7\r
+.equ PORTA6 =6\r
+.equ PORTA5 =5\r
+.equ PORTA4 =4\r
+.equ PORTA3 =3\r
+.equ PORTA2 =2\r
+.equ PORTA1 =1\r
+.equ PORTA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PORTB7 =7\r
+.equ PORTB6 =6\r
+.equ PORTB5 =5\r
+.equ PORTB4 =4\r
+.equ PORTB3 =3\r
+.equ PORTB2 =2\r
+.equ PORTB1 =1\r
+.equ PORTB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PORTC7 =7\r
+.equ PORTC6 =6\r
+.equ PORTC5 =5\r
+.equ PORTC4 =4\r
+.equ PORTC3 =3\r
+.equ PORTC2 =2\r
+.equ PORTC1 =1\r
+.equ PORTC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PORTD7 =7\r
+.equ PORTD6 =6\r
+.equ PORTD5 =5\r
+.equ PORTD4 =4\r
+.equ PORTD3 =3\r
+.equ PORTD2 =2\r
+.equ PORTD1 =1\r
+.equ PORTD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;PORTE\r
+.equ PORTE2 =2\r
+.equ PORTE1 =1\r
+.equ PORTE0 =0\r
+\r
+;DDRE\r
+.equ DDE2 =2\r
+.equ DDE1 =1\r
+.equ DDE0 =0\r
+\r
+;PINE\r
+.equ PINE2 =2\r
+.equ PINE1 =1\r
+.equ PINE0 =0\r
+\r
+;USR (for compatibility with s8515)\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ U2X =1\r
+\r
+;UCSR0A\r
+.equ RXC0 =7\r
+.equ TXC0 =6\r
+.equ UDRE0 =5\r
+.equ FE0 =4\r
+.equ OR0 =3 ; Old name kept for compatibilty\r
+.equ DOR0 =3\r
+.equ PE0 =2 ; New\r
+.equ U2X0 =1\r
+.equ MPCM0 =0\r
+\r
+;UCSR1A\r
+.equ RXC1 =7\r
+.equ TXC1 =6\r
+.equ UDRE1 =5\r
+.equ FE1 =4\r
+.equ OR1 =3 ; Old name kept for compatibilty\r
+.equ DOR1 =3\r
+.equ PE1 =2 ; New\r
+.equ U2X1 =1\r
+.equ MPCM1 =0\r
+\r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;UCR (for compatibility with s8515)\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; Old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+; UCSR0B\r
+.equ RXCIE0 =7\r
+.equ TXCIE0 =6\r
+.equ UDRIE0 =5\r
+.equ RXEN0 =4\r
+.equ TXEN0 =3\r
+.equ CHR90 =2 ; Old name kept for compatibilty\r
+.equ UCSZ02 =2\r
+.equ RXB80 =1\r
+.equ TXB80 =0\r
+\r
+; UCSR1B\r
+.equ RXCIE1 =7\r
+.equ TXCIE1 =6\r
+.equ UDRIE1 =5\r
+.equ RXEN1 =4\r
+.equ TXEN1 =3\r
+.equ CHR91 =2 ; Old name kept for compatibilty\r
+.equ UCSZ12 =2\r
+.equ RXB81 =1\r
+.equ TXB81 =0\r
+ \r
+;UCSR0C New \r
+.equ URSEL0 =7\r
+.equ UMSEL0 =6\r
+.equ UPM01 =5\r
+.equ UPM00 =4\r
+.equ USBS0 =3\r
+.equ UCSZ01 =2\r
+.equ UCSZ00 =1\r
+.equ UCPOL0 =0\r
+\r
+;UCSR1C New \r
+.equ URSEL1 =7\r
+.equ UMSEL1 =6\r
+.equ UPM11 =5\r
+.equ UPM10 =4\r
+.equ USBS1 =3\r
+.equ UCSZ11 =2\r
+.equ UCSZ10 =1\r
+.equ UCPOL1 =0\r
+ \r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ AINBG =6 ; Old mega161\r
+.equ ACBG =6 \r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+\r
+\r
+; Boot loader Lock bit\r
+.equ BLB12 =5\r
+.equ BLB11 =4\r
+.equ BLB02 =3\r
+.equ BLB01 =2\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $488 ; Highest internal data memory (SRAM) address.\r
+ ;(1k RAM + IO + REG)\r
+.equ EEPROMEND = $01ff ; Highest EEPROM address.\r
+ ;(512 byte)\r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $1FFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ ; ( 8k words , 16k byte ) \r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+\r
+\r
+\r
+.equ INT0addr = $002 ; External Interrupt Request 0\r
+.equ INT1addr = $004 ; External Interrupt Request 1\r
+.equ INT2addr = $006 ; External Interrupt Request 2\r
+.equ PCINT0addr = $008 ; Pin Change Interrupt Request 0\r
+.equ PCINT1addr = $00A\r
+.equ TIMER3CAPTaddr = $00C\r
+.equ TIMER3COMPAaddr = $00E\r
+.equ TIMER3COMPBaddr = $010\r
+.equ TIMER3OVFaddr = $012\r
+.equ TIMER2COMPaddr = $014\r
+.equ TIMER2OVFaddr = $016\r
+.equ TIMER1CAPTaddr = $018\r
+.equ TIMER1COMPAaddr = $01A\r
+.equ TIMER1COMPBaddr = $01C\r
+.equ TIMER1OVFaddr = $01E\r
+.equ TIMER0COMPaddr = $020\r
+.equ TIMER0OVFaddr = $022\r
+.equ SPISTCaddr = $024\r
+.equ USART0RXCaddr = $026\r
+.equ USART1RXCaddr = $028\r
+.equ USART0UDREaddr = $02A\r
+.equ USART1UDREaddr = $02C\r
+.equ USART0TXCaddr = $02E\r
+.equ USART1TXCaddr = $030\r
+.equ EE_RDYaddr = $032\r
+.equ ANA_CMPaddr = $034\r
+.equ SPM_RDYaddr = $036\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m163def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega163\r
+;* Date :00.12.12\r
+;* Version :\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega163\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega163\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ; new name for GIMSK \r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ USR =$0b ; For compatibility with S8535\r
+.equ UCSRB =$0a\r
+.equ UCR =$0a ; For compatibility with S8535\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+; GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+; GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+; TIMSK\r
+.equ TOIE0 =0\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+; TIFR\r
+.equ TOV0 =0\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+; SPMCR\r
+.equ ASB =6\r
+.equ ASRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+\r
+.equ TWIE =0\r
+\r
+; MCUCR\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+; MCUSR\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+; TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+; SFIOR\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+; TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+; TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+; TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+; ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+; PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+; DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+; PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+; PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+; DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+; PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+; PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+; DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+; PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+; PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+; DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+; PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+; SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+; SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+; UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+; UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+; ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+; ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+; ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWAR\r
+.equ TWGCE =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND =$1FFF\r
+.equ E2END =$1FF\r
+.equ RAMEND =$45F\r
+\r
+.equ BOOTSTART =$1E00 ;OBSOLETE!!! temporarily kept for compatibility\r
+;.equ LARGEBOOTSTART =$0C00 ;largest boot block is 2KB\r
+;.equ SMALLBOOTSTART =$0F80 ;smallest boot block is 256B\r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+.equ INT0addr=$002 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$004 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$006 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$008 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$00A ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$00C ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$00E ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$010 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$012 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$014 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$016 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$018 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$01A ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$01C ;ADC Interrupt Vector Address\r
+.equ ERDYaddr=$01E ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$020 ;Analog Comparator Interrupt Vector Address\r
+.equ TWSIaddr=$022 ;Irq. vector address for Two-Wire Interface\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m169def.inc"\r
+;* Title : Register/Bit Definitions for the ATmega169\r
+;* Date : June 14th, 2001\r
+;* Version : 2.0\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail : support@atmel.no\r
+;* Target MCU : ATmega169\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;**** Specify Device ****\r
+.device ATmega169\r
+\r
+;*****************************************************************************\r
+; I/O Register Definitions\r
+;*****************************************************************************\r
+\r
+;**** Memory Mapped I/O Register Definitions ****\r
+.equ LCDDR18 = $FE\r
+.equ LCDDR17 = $FD \r
+.equ LCDDR16 = $FC\r
+.equ LCDDR15 = $FB\r
+.equ LCDDR13 = $F9 \r
+.equ LCDDR12 = $F8\r
+.equ LCDDR11 = $F7\r
+.equ LCDDR10 = $F6 \r
+.equ LCDDR8 = $F4\r
+.equ LCDDR7 = $F3\r
+.equ LCDDR6 = $F2\r
+.equ LCDDR5 = $F1 \r
+.equ LCDDR3 = $EF\r
+.equ LCDDR2 = $EE\r
+.equ LCDDR1 = $ED \r
+.equ LCDDR0 = $EC\r
+.equ LCDCCR = $E7\r
+.equ LCDFRR = $E6\r
+.equ LCDCRB = $E5\r
+.equ LCDCRA = $E4\r
+.equ UDR0 = $C6 \r
+.equ UBRR0H = $C5 \r
+.equ UBRR0L = $C4 \r
+.equ UCSR0C = $C2\r
+.equ UCSR0B = $C1\r
+.equ UCSR0A = $C0\r
+.equ USIDR = $BA\r
+.equ USISR = $B9\r
+.equ USICR = $B8\r
+.equ ASSR = $B6\r
+.equ OCR2A = $B3 \r
+.equ TCNT2 = $B2 \r
+.equ TCCR2A = $B0\r
+.equ OCR1BH = $8B \r
+.equ OCR1BL = $8A \r
+.equ OCR1AH = $89 \r
+.equ OCR1AL = $88 \r
+.equ ICR1H = $87 \r
+.equ ICR1L = $86 \r
+.equ TCNT1H = $85 \r
+.equ TCNT1L = $84 \r
+.equ TCCR1C = $82 \r
+.equ TCCR1B = $81\r
+.equ TCCR1A = $80\r
+.equ DIDR1 = $7F\r
+.equ DIDR0 = $7E\r
+.equ ADMUX = $7C \r
+.equ ADCSRB = $7B\r
+.equ ADCSRA = $7A\r
+.equ ADCH = $79 \r
+.equ ADCL = $78\r
+.equ TIMSK2 = $70\r
+.equ TIMSK1 = $6F\r
+.equ TIMSK0 = $6E\r
+.equ PCMSK1 = $6C\r
+.equ PCMSK0 = $6B \r
+.equ EICRA = $69 \r
+.equ OSCCAL = $66\r
+.equ CLKPR = $61\r
+.equ WDTCR = $60\r
+.equ SREG = $3F\r
+.equ SPH = $3E\r
+.equ SPL = $3D\r
+.equ SPMCSR = $37\r
+.equ MCUCR = $35\r
+.equ MCUSR = $34\r
+.equ SMCR = $33\r
+.equ OCDR = $31\r
+.equ ACSR = $30\r
+.equ SPDR = $2E \r
+.equ SPSR = $2D\r
+.equ SPCR = $2C\r
+.equ GPIOR2 = $2B \r
+.equ GPIOR1 = $2A \r
+.equ OCR0A = $27\r
+.equ TCNT0 = $26 \r
+.equ TCCR0A = $24\r
+.equ GTCCR = $23\r
+.equ EEARH = $22 \r
+.equ EEARL = $21 \r
+.equ EEDR = $20\r
+.equ EECR = $1F\r
+.equ GPIOR0 = $1E \r
+.equ EIMSK = $1D\r
+.equ EIFR = $1C\r
+.equ TIFR2 = $17\r
+.equ TIFR1 = $16\r
+.equ TIFR0 = $15\r
+.equ PORTG = $14\r
+.equ DDRG = $13\r
+.equ PING = $12\r
+.equ PORTF = $11\r
+.equ DDRF = $10\r
+.equ PINF = $0F\r
+.equ PORTE = $0E\r
+.equ DDRE = $0D\r
+.equ PINE = $0C\r
+.equ PORTD = $0B\r
+.equ DDRD = $0A\r
+.equ PIND = $09\r
+.equ PORTC = $08\r
+.equ DDRC = $07\r
+.equ PINC = $06\r
+.equ PORTB = $05\r
+.equ DDRB = $04\r
+.equ PINB = $03\r
+.equ PORTA = $02\r
+.equ DDRA = $01\r
+.equ PINA = $00\r
+\r
+;*****************************************************************************\r
+; Bit Definitions\r
+;*****************************************************************************\r
+\r
+; *** LCDDR18, LCDDR13, LCDDR8, LCDDR3 ***\r
+.equ SEG24 = 0 \r
+\r
+; *** LCDSR17, LCDSR12, LCDSR7, LCDSR2 ***\r
+.equ SEG23 = 7 \r
+.equ SEG22 = 6\r
+.equ SEG21 = 5\r
+.equ SEG20 = 4\r
+.equ SEG19 = 3\r
+.equ SEG18 = 2\r
+.equ SEG17 = 1\r
+.equ SEG16 = 0\r
+\r
+; *** LCDSR16, LCDSR11, LCDSR6, LCDSR1 ***\r
+.equ SEG15 = 7 \r
+.equ SEG14 = 6\r
+.equ SEG13 = 5\r
+.equ SEG12 = 4\r
+.equ SEG11 = 3\r
+.equ SEG10 = 2\r
+.equ SEG9 = 1\r
+.equ SEG8 = 0\r
+ \r
+; *** LCDSR15, LCDSR10, LCDSR5, LCDSR0 ***\r
+.equ SEG7 = 7 \r
+.equ SEG6 = 6\r
+.equ SEG5 = 5\r
+.equ SEG4 = 4\r
+.equ SEG3 = 3\r
+.equ SEG2 = 2\r
+.equ SEG1 = 1\r
+.equ SEG0 = 0\r
+\r
+; *** LCDCCR ***\r
+.equ LCDCC3 = 3 \r
+.equ LCDCC2 = 2\r
+.equ LCDCC1 = 1\r
+.equ LCDCC0 = 0\r
+\r
+; *** LCDFRR *** \r
+.equ LCDPS2 = 6 \r
+.equ LCDPS1 = 5\r
+.equ LCDPS0 = 4\r
+.equ LCDCD2 = 2\r
+.equ LCDCD1 = 1\r
+.equ LCDCD0 = 0\r
+ \r
+; *** LCDCRB ***\r
+.equ LCDCS = 7 \r
+.equ LCDB2 = 6\r
+.equ LCDMUX1 = 5 \r
+.equ LCDMUX0 = 4\r
+.equ LCDPM2 = 2\r
+.equ LCDPM1 = 1\r
+.equ LCDPM0 = 0\r
+ \r
+; *** LCDCRA ***\r
+.equ LCDEN = 7 \r
+.equ LCDAB = 6 \r
+.equ LCDIF = 4\r
+.equ LCDIE = 3\r
+.equ LCDBL = 0\r
+\r
+; *** UCSR0C ***\r
+.equ UMSEL0 = 6 \r
+.equ UPM01 = 5\r
+.equ UPM00 = 4\r
+.equ USBS0 = 3\r
+.equ UCSZ01 = 2\r
+.equ UCSZ00 = 1\r
+.equ UCPOL0 = 0\r
+\r
+; *** UCSR0B ***\r
+.equ RXCIE0 = 7 \r
+.equ TXCIE0 = 6\r
+.equ UDRIE0 = 5\r
+.equ RXEN0 = 4\r
+.equ TXEN0 = 3\r
+.equ UCSZ02 = 2\r
+.equ RXB80 = 1\r
+.equ TXB80 = 0\r
+\r
+; *** UCSR0A ***\r
+.equ RXC0 = 7 \r
+.equ TXC0 = 6\r
+.equ UDRE0 = 5\r
+.equ FE0 = 4\r
+.equ DOR0 = 3\r
+.equ PE0 = 2\r
+.equ U2X0 = 1\r
+.equ MPCM0 = 0\r
+\r
+;*** USISR ***\r
+.equ USISIF = 7 \r
+.equ USIOIF = 6\r
+.equ USIPF = 5\r
+.equ USIDC = 4\r
+.equ USICNT3 = 3\r
+.equ USICNT2 = 2\r
+.equ USICNT1 = 1\r
+.equ USICNT0 = 0\r
+\r
+; *** USICR ***\r
+.equ USISIE = 7 \r
+.equ USIOIE = 6\r
+.equ USIWM1 = 5\r
+.equ USIWM0 = 4\r
+.equ USICS1 = 3\r
+.equ USICS0 = 2\r
+.equ USICLK = 1\r
+.equ USITC = 0\r
+ \r
+; *** ASSR ***\r
+.equ EXCLK = 4\r
+.equ AS2 = 3 \r
+.equ TCN2UB = 2\r
+.equ OCR2UB = 1\r
+.equ TCR2UB = 0\r
+\r
+; *** TCCR2A ***\r
+.equ FOC2 = 7 \r
+.equ WGM20 = 6\r
+.equ COM2A1 = 5\r
+.equ COM2A0 = 4\r
+.equ WGM21 = 3\r
+.equ CS22 = 2\r
+.equ CS21 = 1\r
+.equ CS20 = 0\r
+\r
+; *** TCCR1C ***\r
+.equ FOC1A = 7 \r
+.equ FOC1B = 6\r
+\r
+; *** TCCR1B ***\r
+.equ ICNC1 = 7 \r
+.equ ICES1 = 6\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+; *** TCCR1A ***\r
+.equ COM1A1 = 7 \r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ COM1C1 = 3\r
+.equ COM1C0 = 2\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+; *** DIDR1 ***\r
+.equ ADC7D = 7 \r
+.equ ADC6D = 6\r
+.equ ADC5D = 5\r
+.equ ADC4D = 4\r
+.equ ADC3D = 3\r
+.equ ADC2D = 2\r
+.equ ADC1D = 1\r
+.equ ADC0D = 0\r
+\r
+; *** DIDR0 ***\r
+.equ AIN1D = 1 \r
+.equ AIN0D = 0\r
+\r
+; *** ADMUX ***\r
+.equ REFS1 = 7 \r
+.equ REFS0 = 6\r
+.equ ADLAR = 5\r
+.equ MUX4 = 4\r
+.equ MUX3 = 3\r
+.equ MUX2 = 2\r
+.equ MUX1 = 1\r
+.equ MUX0 = 0\r
+\r
+; *** ADCSRB ***\r
+.equ ADHSM = 7 \r
+.equ ACME = 6\r
+.equ ADTS2 = 2\r
+.equ ADTS1 = 1\r
+.equ ADTS0 = 0\r
+\r
+; *** ADCSRA ***\r
+.equ ADEN = 7 \r
+.equ ADSC = 6\r
+.equ ADRF = 5\r
+.equ ADIF = 4\r
+.equ ADIE = 3\r
+.equ ADPS2 = 2\r
+.equ ADPS1 = 1\r
+.equ ADPS0 = 0\r
+\r
+; *** TIMSK2 ***\r
+.equ OCIE2A = 1\r
+.equ TOIE2 = 0\r
+\r
+; *** TIMSK1 ***\r
+.equ ICIE1 = 5 \r
+.equ OCIE1B = 2\r
+.equ OCIE1A = 1\r
+.equ TOIE1 = 0\r
+\r
+; *** TIMSK0 ***\r
+.equ OCIE0A = 1\r
+.equ TOIE0 = 0\r
+\r
+; *** PCMSK1 ***\r
+.equ PCINT15 = 7 \r
+.equ PCINT14 = 6\r
+.equ PCINT13 = 5\r
+.equ PCINT12 = 4\r
+.equ PCINT11 = 3\r
+.equ PCINT10 = 2\r
+.equ PCINT9 = 1\r
+.equ PCINT8 = 0\r
+\r
+; *** PCMSK0 ***\r
+.equ PCINT7 = 7 \r
+.equ PCINT6 = 6\r
+.equ PCINT5 = 5\r
+.equ PCINT4 = 4\r
+.equ PCINT3 = 3\r
+.equ PCINT2 = 2\r
+.equ PCINT1 = 1\r
+.equ PCINT0 = 0\r
+\r
+; *** EICRA ***\r
+.equ ISC01 = 1\r
+.equ ISC00 = 0\r
+\r
+; *** CLKPR ***\r
+.equ CLKPCE = 7 \r
+.equ CLKPS3 = 3\r
+.equ CLKPS2 = 2\r
+.equ CLKPS1 = 1\r
+.equ CLKPS0 = 0\r
+\r
+; *** WDTCR ***\r
+.equ WDCE = 4 \r
+.equ WDE = 3\r
+.equ WDP2 = 2\r
+.equ WDP1 = 1\r
+.equ WDP0 = 0\r
+\r
+; *** SREG ***\r
+.equ I = 7 \r
+.equ T = 6\r
+.equ H = 5\r
+.equ S = 4\r
+.equ V = 3\r
+.equ N = 2\r
+.equ Z = 1\r
+.equ C = 0\r
+\r
+; *** SPH ***\r
+.equ SP15 = 7 \r
+.equ SP14 = 6\r
+.equ SP13 = 5\r
+.equ SP12 = 4\r
+.equ SP11 = 3\r
+.equ SP10 = 2\r
+.equ SP9 = 1\r
+.equ SP8 = 0\r
+\r
+; *** SPL ***\r
+.equ SP7 = 7 \r
+.equ SP6 = 6\r
+.equ SP5 = 5\r
+.equ SP4 = 4\r
+.equ SP3 = 3\r
+.equ SP2 = 2\r
+.equ SP1 = 1\r
+.equ SP0 = 0\r
+\r
+; *** SPMCSR ***\r
+.equ SPMIE = 7 \r
+.equ RWWSB = 6\r
+.equ RWWSRE = 4\r
+.equ BLBSET = 3\r
+.equ PGWRT = 2\r
+.equ PGERS = 1\r
+.equ SPMEN = 0\r
+\r
+; *** MCUCR ***\r
+.equ JTD = 7 \r
+.equ PUD = 4\r
+.equ IVSEL = 1\r
+.equ IVCE = 0\r
+\r
+; *** MCUSR ***\r
+.equ JTRF = 4 \r
+.equ WDRF = 3\r
+.equ BORF = 2\r
+.equ EXTRF = 1\r
+.equ PORF = 0\r
+\r
+; *** SMCR ***\r
+.equ SM2 = 3 \r
+.equ SM1 = 2\r
+.equ SM0 = 1\r
+.equ SE = 0\r
+\r
+; *** OCDR ***\r
+.equ IDRD = 7 \r
+.equ OCD = 7\r
+.equ OCDR6 = 6\r
+.equ OCDR5 = 5\r
+.equ OCDR4 = 4\r
+.equ OCDR3 = 3\r
+.equ OCDR2 = 2\r
+.equ OCDR1 = 1\r
+.equ OCDR0 = 0\r
+\r
+; *** ACSR ***\r
+.equ ACD = 7 \r
+.equ ACBG = 6\r
+.equ ACO = 5\r
+.equ ACI = 4\r
+.equ ACIE = 3\r
+.equ ACIC = 2\r
+.equ ACIS1 = 1\r
+.equ ACIS0 = 0\r
+\r
+; *** SPSR ***\r
+.equ SPIF = 7 \r
+.equ WCOL = 6\r
+.equ SPI2X = 0\r
+\r
+; *** SPCR ***\r
+.equ SPIE = 7 \r
+.equ SPE = 6\r
+.equ DORD = 5\r
+.equ MSTR = 4\r
+.equ CPOL = 3\r
+.equ CPHA = 2\r
+.equ SPR1 = 1\r
+.equ SPR0 = 0\r
+\r
+; *** TCCR0A ***\r
+.equ FOC0A = 7 \r
+.equ WGM00 = 6\r
+.equ COM0A1 = 5\r
+.equ COM0A0 = 4\r
+.equ WGM01 = 3\r
+.equ CS02 = 2\r
+.equ CS01 = 1\r
+.equ CS00 = 0\r
+\r
+; *** GTCCR ***\r
+.equ TSM = 7 \r
+.equ PSR2 = 1\r
+.equ PSR10 = 0\r
+ \r
+; To make tim8pwm_def.inc file\r
+; part independent. \r
+.equ PSR0 = PSR10 \r
+.equ PSR1 = PSR10\r
+ \r
+; *** EECR ***\r
+.equ EERIE = 3 \r
+.equ EEMWE = 2\r
+.equ EEWE = 1\r
+.equ EERE = 0\r
+\r
+; *** EIMSK ***\r
+.equ PCIE1 = 7\r
+.equ PCIE0 = 6\r
+.equ INT0 = 0\r
+\r
+; *** EIFR ***\r
+.equ PCIF1 = 7\r
+.equ PCIF0 = 6\r
+.equ INTF0 = 0\r
+\r
+; *** TIFR2 ***\r
+.equ OCF2A = 1\r
+.equ TOV2 = 0\r
+\r
+; *** TIFR1 ***\r
+.equ ICF1 = 5 \r
+.equ OCF1B = 2\r
+.equ OCF1A = 1\r
+.equ TOV1 = 0\r
+\r
+; *** TIFR0 ***\r
+.equ OCF0A = 1\r
+.equ TOV0 = 0\r
+\r
+; *** PORTG ***\r
+.equ PORTG5 = 5\r
+.equ PORTG4 = 4\r
+.equ PORTG3 = 3\r
+.equ PORTG2 = 2\r
+.equ PORTG1 = 1\r
+.equ PORTG0 = 0\r
+\r
+; *** DDRG ***\r
+.equ DDG4 = 4\r
+.equ DDG3 = 3\r
+.equ DDG2 = 2\r
+.equ DDG1 = 1\r
+.equ DDG0 = 0\r
+\r
+; *** PING ***\r
+.equ PING5 = 5\r
+.equ PING4 = 4\r
+.equ PING3 = 3\r
+.equ PING2 = 2\r
+.equ PING1 = 1\r
+.equ PING0 = 0\r
+\r
+; *** PORTF ***\r
+.equ PORTF7 = 7 \r
+.equ PORTF6 = 6\r
+.equ PORTF5 = 5\r
+.equ PORTF4 = 4\r
+.equ PORTF3 = 3\r
+.equ PORTF2 = 2\r
+.equ PORTF1 = 1\r
+.equ PORTF0 = 0\r
+\r
+; *** DDRF ***\r
+.equ DDF7 = 7 \r
+.equ DDF6 = 6\r
+.equ DDF5 = 5\r
+.equ DDF4 = 4\r
+.equ DDF3 = 3\r
+.equ DDF2 = 2\r
+.equ DDF1 = 1\r
+.equ DDF0 = 0\r
+\r
+; *** PINF ***\r
+.equ PINF7 = 7 \r
+.equ PINF6 = 6\r
+.equ PINF5 = 5\r
+.equ PINF4 = 4\r
+.equ PINF3 = 3\r
+.equ PINF2 = 2\r
+.equ PINF1 = 1\r
+.equ PINF0 = 0\r
+\r
+; *** PORTE ***\r
+.equ PORTE7 = 7 \r
+.equ PORTE6 = 6\r
+.equ PORTE5 = 5\r
+.equ PORTE4 = 4\r
+.equ PORTE3 = 3\r
+.equ PORTE2 = 2\r
+.equ PORTE1 = 1\r
+.equ PORTE0 = 0\r
+\r
+; *** DDRE ***\r
+.equ DDE7 = 7 \r
+.equ DDE6 = 6\r
+.equ DDE5 = 5\r
+.equ DDE4 = 4\r
+.equ DDE3 = 3\r
+.equ DDE2 = 2\r
+.equ DDE1 = 1\r
+.equ DDE0 = 0\r
+\r
+; *** PINE ***\r
+.equ PINE7 = 7 \r
+.equ PINE6 = 6\r
+.equ PINE5 = 5\r
+.equ PINE4 = 4\r
+.equ PINE3 = 3\r
+.equ PINE2 = 2\r
+.equ PINE1 = 1\r
+.equ PINE0 = 0\r
+\r
+; *** PORTD ***\r
+.equ PORTD7 = 7 \r
+.equ PORTD6 = 6\r
+.equ PORTD5 = 5\r
+.equ PORTD4 = 4\r
+.equ PORTD3 = 3\r
+.equ PORTD2 = 2\r
+.equ PORTD1 = 1\r
+.equ PORTD0 = 0\r
+\r
+; *** DDRD ***\r
+.equ DDD7 = 7 \r
+.equ DDD6 = 6\r
+.equ DDD5 = 5\r
+.equ DDD4 = 4\r
+.equ DDD3 = 3\r
+.equ DDD2 = 2\r
+.equ DDD1 = 1\r
+.equ DDD0 = 0\r
+\r
+; *** PIND ***\r
+.equ PIND7 = 7 \r
+.equ PIND6 = 6\r
+.equ PIND5 = 5\r
+.equ PIND4 = 4\r
+.equ PIND3 = 3\r
+.equ PIND2 = 2\r
+.equ PIND1 = 1\r
+.equ PIND0 = 0\r
+\r
+; *** PORTC ***\r
+.equ PORTC7 = 7 \r
+.equ PORTC6 = 6\r
+.equ PORTC5 = 5\r
+.equ PORTC4 = 4\r
+.equ PORTC3 = 3\r
+.equ PORTC2 = 2\r
+.equ PORTC1 = 1\r
+.equ PORTC0 = 0\r
+\r
+; *** DDRC ***\r
+.equ DDC7 = 7 \r
+.equ DDC6 = 6\r
+.equ DDC5 = 5\r
+.equ DDC4 = 4\r
+.equ DDC3 = 3\r
+.equ DDC2 = 2\r
+.equ DDC1 = 1\r
+.equ DDC0 = 0\r
+\r
+; *** PINC ***\r
+.equ PINC7 = 7 \r
+.equ PINC6 = 6\r
+.equ PINC5 = 5\r
+.equ PINC4 = 4\r
+.equ PINC3 = 3\r
+.equ PINC2 = 2\r
+.equ PINC1 = 1\r
+.equ PINC0 = 0\r
+\r
+; *** PORTB ***\r
+.equ PORTB7 = 7 \r
+.equ PORTB6 = 6\r
+.equ PORTB5 = 5\r
+.equ PORTB4 = 4\r
+.equ PORTB3 = 3\r
+.equ PORTB2 = 2\r
+.equ PORTB1 = 1\r
+.equ PORTB0 = 0\r
+\r
+; *** DDRB ***\r
+.equ DDB7 = 7 \r
+.equ DDB6 = 6\r
+.equ DDB5 = 5\r
+.equ DDB4 = 4\r
+.equ DDB3 = 3\r
+.equ DDB2 = 2\r
+.equ DDB1 = 1\r
+.equ DDB0 = 0\r
+\r
+; *** PINB ***\r
+.equ PINB7 = 7 \r
+.equ PINB6 = 6\r
+.equ PINB5 = 5\r
+.equ PINB4 = 4\r
+.equ PINB3 = 3\r
+.equ PINB2 = 2\r
+.equ PINB1 = 1\r
+.equ PINB0 = 0\r
+\r
+; *** PORTA ***\r
+.equ PORTA7 = 7 \r
+.equ PORTA6 = 6\r
+.equ PORTA5 = 5\r
+.equ PORTA4 = 4\r
+.equ PORTA3 = 3\r
+.equ PORTA2 = 2\r
+.equ PORTA1 = 1\r
+.equ PORTA0 = 0\r
+\r
+; *** DDRA ***\r
+.equ DDA7 = 7 \r
+.equ DDA6 = 6\r
+.equ DDA5 = 5\r
+.equ DDA4 = 4\r
+.equ DDA3 = 3\r
+.equ DDA2 = 2\r
+.equ DDA1 = 1\r
+.equ DDA0 = 0\r
+\r
+; *** PINA ***\r
+.equ PINA7 = 7 \r
+.equ PINA6 = 6\r
+.equ PINA5 = 5\r
+.equ PINA4 = 4\r
+.equ PINA3 = 3\r
+.equ PINA2 = 2\r
+.equ PINA1 = 1\r
+.equ PINA0 = 0\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $4ff ; Highest internal data memory (SRAM) address.\r
+ ;(1k RAM + IO + REG)\r
+.equ EEPROMEND = $01ff ; Highest EEPROM address.\r
+ ;(512 byte)\r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $1FFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ ; ( 8k words , 16k byte ) \r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+\r
+;**** Page Size ****\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+;**** Interrupt Vectors **** \r
+.equ INT0addr =$002 ;External Interrupt0 Interrupt Address\r
+.equ PCINT0addr =$004 ;Pin Change Interrupt0 Interrupt Address \r
+.equ PCINT1addr =$006 ;Pin Change Interrupt1 Interrupt Address\r
+.equ CMP2addr =$008 \r
+.equ OC2addr =$008 ;Timer/Counter2 Compare Match Interrupt Address\r
+.equ OVF2addr =$00a ;Overflow1 Interrupt Address\r
+.equ ICP1addr =$00c ;Input Capture1 Interrupt Address\r
+.equ OC1Aaddr =$00e ;Output Compare1A Interrupt Address\r
+.equ OC1Baddr =$010 ;Output Compare1B Interrupt Address \r
+.equ OVF1addr =$012 ;Overflow1 Interrupt Address\r
+.equ CMP0addr =$014 \r
+.equ OC0addr =$014 ;Timer/Counter0 Compare Match Interrupt Address\r
+.equ OVF0addr =$016 ;Overflow0 Interrupt Address\r
+.equ SPIaddr =$018 ;SPI Interrupt Address\r
+.equ URXC0addr =$01a ;UART Receive Complete Interrupt Address\r
+.equ UDRE0addr =$01c ;UART Data Register Empty Interrupt Address\r
+.equ UTXC0addr =$01e ;UART Transmit Complete Interrupt Address\r
+.equ USI_STARTaddr=$020 ;Universal Serial Bus Start Interrupt Address \r
+.equ USI_OVFaddr =$022 ;Universal Serial Bus Overflow Interrupt Address \r
+.equ ACIaddr =$024 ;Analog Comparator Interrupt Address\r
+.equ ADCCaddr =$026 ;ADC Conversion Complete Interrupt Address\r
+.equ ERDYaddr =$028 ;EEPROM write complete Interrupt Address\r
+.equ SPMRaddr =$02a ;Store Program Memory Ready Interrupt Address\r
+.equ LCDSFaddr =$02c ;LCD Start of Frame Interrupt Address\r
+\r
+;for compatibility with s8515\r
+.equ URXCaddr=$01a ;UART Receive Complete Interrupt \r
+.equ UDREaddr=$01e ;UART Data Register Empty Interrupt \r
+.equ UTXCaddr=$022 ;UART Transmit Complete Interrupt \r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m16def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega16\r
+;* Date :07.09.2001\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega16\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega16\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ OCR0 =$3c \r
+.equ GICR =$3b ; New name for GIMSK\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ I2CR =$36\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ MCUCSR =$34 ; New name for MCUSR\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20\r
+.equ UBRRH =$20 ; New name for UBRRHI\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ USR =$0b ; For compatibility with S8535\r
+.equ UCSRB =$0a\r
+.equ UCR =$0a ; For compatibility with S8535\r
+.equ UCSRC =$20 ; Note! UCSRC equals UBRRH \r
+.equ UBRR =$09\r
+.equ UBRRL =$09 ; New name for UBRR\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+.equ I2DR =$03\r
+.equ I2AR =$02\r
+.equ I2SR =$01\r
+.equ I2BR =$00\r
+\r
+;***** Bit Definitions\r
+\r
+; GIMSK / GICR\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5 \r
+.equ IVSEL =1 \r
+.equ IVCE =0 \r
+ \r
+; GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5 \r
+\r
+; TIMSK\r
+.equ TOIE0 =0\r
+.equ OCIE0 =1 \r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+; TIFR\r
+.equ TOV0 =0\r
+.equ OCF0 =1 \r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+; SPMCR\r
+.equ SPMIE =7\r
+.equ ASB =6\r
+.equ ASRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+ \r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+\r
+.equ TWIE =0\r
+\r
+; MCUCR\r
+ \r
+.equ SM2 =7 \r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+; MCUSR\r
+.equ ISC2 =6 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+; TCCR0\r
+.equ FOC0 =7 \r
+.equ PWM0 =6 ;OBSOLETE! Use WGM00\r
+.equ WGM00 =6\r
+.equ COM01 =5 \r
+.equ COM00 =4 \r
+.equ CTC0 =3 ;OBSOLETE! Use WGM01\r
+.equ WGM01 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+; SFIOR\r
+.equ ADTS2 =7 \r
+.equ ADTS1 =6 \r
+.equ ADTS0 =5 \r
+.equ ADHSM =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+; TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 =1\r
+.equ WGM10 =0\r
+\r
+; TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ CTC1 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 =4\r
+.equ WGM12 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+; TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ WGM20 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ WGM21 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+; ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+; PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+; DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+; PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+; PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+; DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+; PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+; PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+; DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+; PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+; PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+; DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+; PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+; SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+; SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+; UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ DOR =3 ;New name for OR\r
+.equ PE =2 \r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+; UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ UCSZ2 =2 ; New name for CHR9\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7 \r
+.equ UMSEL =6 \r
+.equ UPM1 =5 \r
+.equ UPM0 =4 \r
+.equ USBS =3 \r
+.equ UCSZ1 =2 \r
+.equ UCSZ0 =1 \r
+.equ UCPOL =0 \r
+\r
+; ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+; ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+; ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADATE =5 \r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWAR\r
+.equ TWGCE =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$45F\r
+\r
+.equ BOOTSTART =$1E00 ;OBSOLETE!!! temporarily kept for compatibility\r
+;.equ LARGEBOOTSTART =$0C00 ;largest boot block is 2KB\r
+;.equ SMALLBOOTSTART =$0F80 ;smallest boot block is 256B\r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+.equ FLASHEND =$1fff\r
+\r
+.equ INT0addr=$002 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$004 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$006 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$008 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$00A ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$00C ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$00E ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$010 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$012 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$014 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$016 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$018 ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$01A ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$01C ;ADC Interrupt Vector Address\r
+.equ ERDYaddr=$01E ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$020 ;Analog Comparator Interrupt Vector Address\r
+.equ TWIaddr =$022 ;Irq. vector address for Two-Wire Interface\r
+.equ INT2addr=$024 ;External Interrupt2 Vector Address\r
+.equ OC0addr =$026 ;Output Compare0 Interrupt Vector Address\r
+.equ SPMRaddr=$028 ;Store Program Memory Ready Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m323def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega323\r
+;* Date :99.08.25\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega323\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega323\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ OCR0 =$3c\r
+.equ GIMSK =$3b ; For compatibility, keep both names until further\r
+.equ GICR =$3b ; new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRH =$20 ; Note! UCSRC equals UBRRH\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UCSRC =$20 ; Note! UCSRC equals UBRRH\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+\r
+\r
+;***** Bit Definitions\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE0 =0\r
+.equ OCIE0 =1\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+;TIFR\r
+.equ TOV0 =0\r
+.equ OCF0 =1\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ ASB =6\r
+.equ ASRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;MCUCR\r
+.equ SE =7\r
+.equ SM2 =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUCSR\r
+.equ JTD =7 \r
+.equ ISC2 =6\r
+.equ EIH =5\r
+.equ JTRF =4 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ PWM0 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4\r
+.equ CTC10 =3\r
+.equ CTC1 =3 ; Obsolete - Included for backward compatibility\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;SFIOR\r
+.equ RPDD =7\r
+.equ RPDC =6\r
+.equ RPDB =5\r
+.equ RPDA =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ PE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+.equ TWI_TST =1 ;Present in core test mode only. Write Only.\r
+.equ TWIE =0\r
+\r
+; TWAR\r
+.equ TWGCE =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND =$3FFF\r
+.equ E2END =$3FF\r
+.equ RAMEND =$85F\r
+\r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b11111100000000 ;($3F00) smallest boot block is 256W\r
+.equ SECONDBOOTSTART =0b11111000000000 ;($3E00) 2'nd boot block size is 512W\r
+.equ THIRDBOOTSTART =0b11110000000000 ;($3C00) third boot block size is 1KW\r
+.equ LARGEBOOTSTART =0b11100000000000 ;($3800) largest boot block is 2KW\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+\r
+.equ INT0addr=$002 ; External Interrupt0 Vector Address\r
+.equ INT1addr=$004 ; External Interrupt1 Vector Address\r
+.equ INT2addr=$006 ; External Interrupt2 Vector Address\r
+.equ OC2addr =$008 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$00a ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$00c ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$00e ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$010 ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$012 ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr =$014 ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr=$016 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$018 ; SPI Interrupt Vector Address\r
+.equ URXCaddr=$01a ; USART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$01c ; USART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$01e ; USART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$020 ; ADC Interrupt Vector Address\r
+.equ ERDYaddr=$022 ; EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$024 ; Analog Comparator Interrupt Vector Address\r
+.equ TWSIaddr=$026 ; Irq. vector address for Two-Wire Interface\r
+.equ SPMRaddr=$028 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m32def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega32\r
+;* Date :99.08.25\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega32\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega32\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ OCR0 =$3c\r
+.equ GIMSK =$3b ; For compatibility, keep both names until further\r
+.equ GICR =$3b ; new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRH =$20 ; Note! UCSRC equals UBRRH\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UCSRC =$20 ; Note! UCSRC equals UBRRH\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+\r
+\r
+;***** Bit Definitions\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE0 =0\r
+.equ OCIE0 =1\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+;TIFR\r
+.equ TOV0 =0\r
+.equ OCF0 =1\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ ASB =6\r
+.equ ASRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;MCUCR\r
+.equ SE =7\r
+.equ SM2 =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUCSR\r
+.equ JTD =7 \r
+.equ ISC2 =6\r
+.equ EIH =5\r
+.equ JTRF =4 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ PWM0 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4\r
+.equ CTC10 =3\r
+.equ CTC1 =3 ; Obsolete - Included for backward compatibility\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;SFIOR\r
+.equ RPDD =7\r
+.equ RPDC =6\r
+.equ RPDB =5\r
+.equ RPDA =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ PE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+.equ TWI_TST =1 ;Present in core test mode only. Write Only.\r
+.equ TWIE =0\r
+\r
+; TWAR\r
+.equ TWGCE =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND =$3FFF\r
+.equ E2END =$3FF\r
+.equ RAMEND =$85F\r
+\r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b11111100000000 ;($3F00) smallest boot block is 256W\r
+.equ SECONDBOOTSTART =0b11111000000000 ;($3E00) 2'nd boot block size is 512W\r
+.equ THIRDBOOTSTART =0b11110000000000 ;($3C00) third boot block size is 1KW\r
+.equ LARGEBOOTSTART =0b11100000000000 ;($3800) largest boot block is 2KW\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+\r
+.equ INT0addr=$002 ; External Interrupt0 Vector Address\r
+.equ INT1addr=$004 ; External Interrupt1 Vector Address\r
+.equ INT2addr=$006 ; External Interrupt2 Vector Address\r
+.equ OC2addr =$008 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$00a ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$00c ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$00e ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$010 ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$012 ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr =$014 ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr=$016 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$018 ; SPI Interrupt Vector Address\r
+.equ URXCaddr=$01a ; USART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$01c ; USART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$01e ; USART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$020 ; ADC Interrupt Vector Address\r
+.equ ERDYaddr=$022 ; EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$024 ; Analog Comparator Interrupt Vector Address\r
+.equ TWSIaddr=$026 ; Irq. vector address for Two-Wire Interface\r
+.equ SPMRaddr=$028 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number : AVR000\r
+;* File Name : "m64def.inc"\r
+;* Title : Register/Bit Definitions for the ATmega604\r
+;* Date : April 16th, 2002\r
+;* Version : 1.0\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail : support@atmel.no\r
+;* Target MCU : ATmega64\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;**** Specify Device ****\r
+.device ATmega64\r
+\r
+;*****************************************************************************\r
+; I/O Register Definitions\r
+;*****************************************************************************\r
+\r
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****\r
+.equ UCSR1C = $9D\r
+.equ UDR1 = $9C\r
+.equ UCSR1A = $9B\r
+.equ UCSR1B = $9A\r
+.equ UBRR1L = $99\r
+.equ UBRR1H = $98\r
+.equ UCSR0C = $95\r
+.equ UBRR0H = $90\r
+.equ ADCSRB = $8E\r
+.equ TCCR3C = $8C\r
+.equ TCCR3A = $8B\r
+.equ TCCR3B = $8A\r
+.equ TCNT3H = $89\r
+.equ TCNT3L = $88\r
+.equ OCR3AH = $87\r
+.equ OCR3AL = $86\r
+.equ OCR3BH = $85\r
+.equ OCR3BL = $84\r
+.equ OCR3CH = $83\r
+.equ OCR3CL = $82\r
+.equ ICR3H = $81\r
+.equ ICR3L = $80\r
+.equ ETIMSK = $7D\r
+.equ ETIFR = $7C\r
+.equ TCCR1C = $7A\r
+.equ OCR1CH = $79\r
+.equ OCR1CL = $78\r
+.equ I2CR = $74\r
+.equ I2DR = $73\r
+.equ I2AR = $72\r
+.equ I2SR = $71\r
+.equ I2BR = $70\r
+.equ TWCR = $74\r
+.equ TWDR = $73\r
+.equ TWAR = $72\r
+.equ TWSR = $71\r
+.equ TWBR = $70\r
+.equ OSCCAL = $6F\r
+.equ XMCRA = $6D\r
+.equ XMCRB = $6C\r
+.equ EICRA = $6A\r
+.equ SPMCSR = $68\r
+.equ SPMCR = $68 ; old name for SPMCSR\r
+.equ PORTG = $65\r
+.equ DDRG = $64\r
+.equ PING = $63\r
+.equ PORTF = $62\r
+.equ DDRF = $61\r
+\r
+;**** I/O Register Definitions ($3F-$00) ****\r
+.equ SREG = $3F\r
+.equ SPH = $3E\r
+.equ SPL = $3D\r
+.equ XDIV = $3C\r
+.equ EICRB = $3A\r
+.equ EIMSK = $39\r
+.equ GIMSK = $39 ; old name for EIMSK\r
+.equ GICR = $39 ; old name for EIMSK\r
+.equ EIFR = $38\r
+.equ GIFR = $38 ; old name for EIFR\r
+.equ TIMSK = $37\r
+.equ TIFR = $36\r
+.equ MCUCR = $35\r
+.equ MCUCSR = $34\r
+.equ TCCR0 = $33\r
+.equ TCNT0 = $32\r
+.equ OCR0 = $31\r
+.equ ASSR = $30\r
+.equ TCCR1A = $2F\r
+.equ TCCR1B = $2E\r
+.equ TCNT1H = $2D\r
+.equ TCNT1L = $2C\r
+.equ OCR1AH = $2B\r
+.equ OCR1AL = $2A\r
+.equ OCR1BH = $29\r
+.equ OCR1BL = $28\r
+.equ ICR1H = $27\r
+.equ ICR1L = $26\r
+.equ TCCR2 = $25\r
+.equ TCNT2 = $24\r
+.equ OCR2 = $23\r
+.equ OCDR = $22 ; New\r
+.equ WDTCR = $21\r
+.equ SFIOR = $20 ; New\r
+.equ EEARH = $1F\r
+.equ EEARL = $1E\r
+.equ EEDR = $1D\r
+.equ EECR = $1C\r
+.equ PORTA = $1B\r
+.equ DDRA = $1A\r
+.equ PINA = $19\r
+.equ PORTB = $18\r
+.equ DDRB = $17\r
+.equ PINB = $16\r
+.equ PORTC = $15\r
+.equ DDRC = $14 ; New\r
+.equ PINC = $13 ; New\r
+.equ PORTD = $12\r
+.equ DDRD = $11\r
+.equ PIND = $10\r
+.equ SPDR = $0F\r
+.equ SPSR = $0E\r
+.equ SPCR = $0D\r
+.equ UDR0 = $0C\r
+.equ UCSR0A = $0B\r
+.equ UCSR0B = $0A\r
+.equ UBRR0L = $09\r
+.equ ACSR = $08\r
+.equ ADMUX = $07\r
+.equ ADCSRA = $06 \r
+.equ ADCSR = $06\r
+.equ ADCH = $05\r
+.equ ADCL = $04\r
+.equ PORTE = $03\r
+.equ DDRE = $02\r
+.equ PINE = $01\r
+.equ PINF = $00\r
+\r
+\r
+;*****************************************************************************\r
+; Bit Definitions\r
+;*****************************************************************************\r
+\r
+; **** MCU Control ****\r
+; **** MCUCR ****\r
+.equ SRE = 7 \r
+.equ SRW10 = 6\r
+.equ SE = 5\r
+.equ SM1 = 4\r
+.equ SM0 = 3\r
+.equ SM2 = 2\r
+.equ IVSEL = 1\r
+.equ IVCE = 0\r
+\r
+; **** MCUCSR ****\r
+.equ JTD = 7 \r
+.equ JTRF = 4 \r
+.equ WDRF = 3\r
+.equ BORF = 2\r
+.equ EXTRF = 1\r
+.equ PORF = 0\r
+\r
+; **** XMCRA ****\r
+.equ SRL2 = 6 \r
+.equ SRL1 = 5\r
+.equ SRL0 = 4\r
+.equ SRW01 = 3\r
+.equ SRW00 = 2\r
+.equ SRW11 = 1\r
+\r
+; **** XMCRB ****\r
+.equ XMBK = 7 \r
+.equ XMM2 = 2\r
+.equ XMM1 = 1\r
+.equ XMM0 = 0\r
+\r
+; **** SPMCSR ****\r
+.equ SPMIE = 7 \r
+.equ ASB = 6 ; backwards compatiblity\r
+.equ ASRE = 4 ; backwards compatiblity\r
+.equ RWWSB = 6\r
+.equ RWWSRE = 4 \r
+.equ BLBSET = 3\r
+.equ PGWRT = 2\r
+.equ PGERS = 1\r
+.equ SPMEN = 0\r
+\r
+; **** OCDR ****\r
+.equ IDRD = 7 \r
+.equ OCDR6 = 6\r
+.equ OCDR5 = 5\r
+.equ OCDR4 = 4 \r
+.equ OCDR3 = 3\r
+.equ OCDR2 = 2\r
+.equ OCDR1 = 1\r
+.equ OCDR0 = 0\r
+\r
+; **** XDIV ****\r
+.equ XDIVEN = 7 \r
+.equ XDIV6 = 6\r
+.equ XDIV5 = 5\r
+.equ XDIV4 = 4\r
+.equ XDIV3 = 3\r
+.equ XDIV2 = 2\r
+.equ XDIV1 = 1\r
+.equ XDIV0 = 0\r
+\r
+; **** SFIOR ****\r
+.equ TSM = 7 \r
+.equ ADHSM = 4\r
+.equ ACME = 3\r
+.equ PUD = 2\r
+.equ PSR0 = 1\r
+.equ PSR1 = 0\r
+.equ PSR2 = 0\r
+.equ PSR3 = 0\r
+.equ PSR321 = 0 \r
+\r
+; **** Analog to Digital Converter ****\r
+; **** ADCSR ****\r
+.equ ADEN = 7 \r
+.equ ADSC = 6\r
+.equ ADATE = 5\r
+.equ ADFR = 5\r
+.equ ADIF = 4\r
+.equ ADIE = 3\r
+.equ ADPS2 = 2\r
+.equ ADPS1 = 1\r
+.equ ADPS0 = 0\r
+\r
+; **** ADMUX ****\r
+.equ REFS1 = 7 \r
+.equ REFS0 = 6\r
+.equ ADLAR = 5\r
+.equ MUX4 = 4\r
+.equ MUX3 = 3\r
+.equ MUX2 = 2\r
+.equ MUX1 = 1\r
+.equ MUX0 = 0\r
+\r
+; **** ADCSRB ****\r
+.equ ADTS2 = 2 \r
+.equ ADTS1 = 1\r
+.equ ADTS0 = 0 \r
+\r
+;**** Analog Comparator ****\r
+; **** ACSR ****\r
+.equ ACD = 7 \r
+.equ ACBG = 6\r
+.equ ACO = 5\r
+.equ ACI = 4\r
+.equ ACIE = 3\r
+.equ ACIC = 2\r
+.equ ACIS1 = 1\r
+.equ ACIS0 = 0\r
+ \r
+\r
+; **** External Interrupts ****\r
+; **** EIMSK ****\r
+.equ INT7 = 7 \r
+.equ INT6 = 6\r
+.equ INT5 = 5\r
+.equ INT4 = 4\r
+.equ INT3 = 3\r
+.equ INT2 = 2\r
+.equ INT1 = 1\r
+.equ INT0 = 0\r
+\r
+; **** EIFR ****\r
+.equ INTF7 = 7 \r
+.equ INTF6 = 6\r
+.equ INTF5 = 5\r
+.equ INTF4 = 4\r
+.equ INTF3 = 3\r
+.equ INTF2 = 2\r
+.equ INTF1 = 1\r
+.equ INTF0 = 0\r
+\r
+; **** EICRB ****\r
+.equ ISC71 = 7 \r
+.equ ISC70 = 6\r
+.equ ISC61 = 5\r
+.equ ISC60 = 4\r
+.equ ISC51 = 3\r
+.equ ISC50 = 2\r
+.equ ISC41 = 1\r
+.equ ISC40 = 0\r
+\r
+; **** EICRA ****\r
+.equ ISC31 = 7 \r
+.equ ISC30 = 6\r
+.equ ISC21 = 5\r
+.equ ISC20 = 4\r
+.equ ISC11 = 3\r
+.equ ISC10 = 2\r
+.equ ISC01 = 1\r
+.equ ISC00 = 0\r
+\r
+; **** Timer Interrupts ****\r
+; **** TIMSK ****\r
+.equ OCIE2 = 7 \r
+.equ TOIE2 = 6\r
+.equ TICIE1 = 5\r
+.equ OCIE1A = 4\r
+.equ OCIE1B = 3\r
+.equ TOIE1 = 2\r
+.equ OCIE0 = 1\r
+.equ TOIE0 = 0\r
+\r
+; **** ETIMSK ****\r
+.equ TICIE3 = 5 \r
+.equ OCIE3A = 4\r
+.equ OCIE3B = 3\r
+.equ TOIE3 = 2\r
+.equ OCIE3C = 1\r
+.equ OCIE1C = 0\r
+\r
+; **** TIFR ****\r
+.equ OCF2 = 7 \r
+.equ TOV2 = 6\r
+.equ ICF1 = 5\r
+.equ OCF1A = 4\r
+.equ OCF1B = 3\r
+.equ TOV1 = 2\r
+.equ OCF0 = 1\r
+.equ TOV0 = 0\r
+\r
+; **** ETIFR ****\r
+.equ ICF3 = 5 \r
+.equ OCF3A = 4\r
+.equ OCF3B = 3\r
+.equ TOV3 = 2\r
+.equ OCF3C = 1\r
+.equ OCF1C = 0\r
+\r
+; **** Asynchronous Timer ****\r
+; **** ASSR ****\r
+.equ AS0 = 3 \r
+.equ TCN0UB = 2\r
+.equ OCR0UB = 1\r
+.equ TCR0UB = 0\r
+\r
+; **** Timer 0 ****\r
+; **** TCCR0 ****\r
+.equ FOC0 = 7 \r
+.equ PWM0 = 6\r
+.equ WGM00 = 6 \r
+.equ COM01 = 5\r
+.equ COM00 = 4\r
+.equ CTC0 = 3\r
+.equ WGM01 = 3\r
+.equ CS02 = 2\r
+.equ CS01 = 1\r
+.equ CS00 = 0\r
+\r
+; **** Timer 1 ****\r
+; **** TCCR1A ****\r
+.equ COM1A1 = 7 \r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ COM1C1 = 3\r
+.equ COM1C0 = 2\r
+.equ PWM11 = 1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 = 0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+; **** TCCR1B ****\r
+.equ ICNC1 = 7 \r
+.equ ICES1 = 6\r
+.equ CTC11 = 4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 = 3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+; **** TCCR1C ****\r
+.equ FOC1A = 7 \r
+.equ FOC1B = 6\r
+.equ FOC1C = 5\r
+\r
+; **** Timer 2 ****\r
+; **** TCCR2 ****\r
+.equ FOC2 = 7 \r
+.equ PWM2 = 6\r
+.equ WGM20 = 6 \r
+.equ COM21 = 5\r
+.equ COM20 = 4\r
+.equ CTC2 = 3\r
+.equ WGM21 = 3\r
+.equ CS22 = 2\r
+.equ CS21 = 1\r
+.equ CS20 = 0\r
+\r
+; **** Timer 3 ****\r
+; **** TCCR3A ****\r
+.equ COM3A1 = 7 \r
+.equ COM3A0 = 6\r
+.equ COM3B1 = 5\r
+.equ COM3B0 = 4\r
+.equ COM3C1 = 3\r
+.equ COM3C0 = 2\r
+.equ PWM31 = 1 ; OBSOLETE! Use WGM31\r
+.equ PWM30 = 0 ; OBSOLETE! Use WGM30\r
+.equ WGM31 = 1\r
+.equ WGM30 = 0\r
+\r
+; **** TCCR3B **** \r
+.equ ICNC3 = 7 \r
+.equ ICES3 = 6\r
+.equ CTC31 = 4 ; OBSOLETE! Use WGM33\r
+.equ CTC30 = 3 ; OBSOLETE! Use WGM32\r
+.equ WGM33 = 4\r
+.equ WGM32 = 3\r
+.equ CS32 = 2\r
+.equ CS31 = 1\r
+.equ CS30 = 0\r
+\r
+; **** TCCR3C ****\r
+.equ FOC3A = 7 \r
+.equ FOC3B = 6\r
+.equ FOC3C = 5\r
+\r
+; **** Watchdog Timer ****\r
+; **** WDTCR ****\r
+.equ WDCE = 4 \r
+.equ WDTOE = 4 ; For Mega103 compability\r
+.equ WDE = 3\r
+.equ WDP2 = 2\r
+.equ WDP1 = 1\r
+.equ WDP0 = 0\r
+\r
+; **** EEPROM Control Register ****\r
+; **** EECR ****\r
+.equ EERIE = 3 \r
+.equ EEMWE = 2\r
+.equ EEWE = 1\r
+.equ EERE = 0\r
+\r
+; **** USART 0 and USART 1 ****\r
+; **** (UCSRA0/1) ****\r
+.equ RXC = 7 \r
+.equ TXC = 6\r
+.equ UDRE = 5\r
+.equ FE = 4\r
+.equ DOR = 3\r
+.equ PE = 2 ; OBSOLETED!\r
+.equ U2X = 1\r
+.equ MPCM = 0\r
+\r
+; **** (UCSR0A) ****\r
+.equ RXC0 = 7 \r
+.equ TXC0 = 6\r
+.equ UDRE0 = 5\r
+.equ FE0 = 4\r
+.equ DOR0 = 3\r
+.equ UPE0 = 2\r
+.equ U2X0 = 1\r
+.equ MPCM0 = 0\r
+\r
+; **** (UCSR1A) ****\r
+.equ RXC1 = 7 \r
+.equ TXC1 = 6\r
+.equ UDRE1 = 5\r
+.equ FE1 = 4\r
+.equ DOR1 = 3\r
+.equ UPE1 = 2\r
+.equ U2X1 = 1\r
+.equ MPCM1 = 0\r
+\r
+; **** (UCSRB0/1) ****\r
+.equ RXCIE = 7 \r
+.equ TXCIE = 6\r
+.equ UDRIE = 5\r
+.equ RXEN = 4\r
+.equ TXEN = 3\r
+.equ UCSZ2 = 2\r
+.equ RXB8 = 1\r
+.equ TXB8 = 0\r
+\r
+; **** (UCSR0B) ****\r
+.equ RXCIE0 = 7 \r
+.equ TXCIE0 = 6\r
+.equ UDRIE0 = 5\r
+.equ RXEN0 = 4\r
+.equ TXEN0 = 3\r
+.equ UCSZ02 = 2\r
+.equ RXB80 = 1\r
+.equ TXB80 = 0\r
+\r
+; **** (UCSR1B) ****\r
+.equ RXCIE1 = 7 \r
+.equ TXCIE1 = 6\r
+.equ UDRIE1 = 5\r
+.equ RXEN1 = 4\r
+.equ TXEN1 = 3\r
+.equ UCSZ12 = 2\r
+.equ RXB81 = 1\r
+.equ TXB81 = 0\r
+\r
+; **** (UCSRC0/1) ****\r
+.equ UMSEL = 6 \r
+.equ UPM1 = 5\r
+.equ UPM0 = 4\r
+.equ USBS = 3\r
+.equ UCSZ1 = 2\r
+.equ UCSZ0 = 1\r
+.equ UCPOL = 0\r
+\r
+; **** (UCSR0C) ****\r
+.equ UMSEL0 = 6 \r
+.equ UPM01 = 5\r
+.equ UPM00 = 4\r
+.equ USBS0 = 3\r
+.equ UCSZ01 = 2\r
+.equ UCSZ00 = 1\r
+.equ UCPOL0 = 0\r
+\r
+; **** (UCSR1C) ****\r
+.equ UMSEL1 = 6 \r
+.equ UPM11 = 5\r
+.equ UPM10 = 4\r
+.equ USBS1 = 3\r
+.equ UCSZ11 = 2\r
+.equ UCSZ10 = 1\r
+.equ UCPOL1 = 0\r
+\r
+ \r
+; **** SPI ****\r
+; **** SPCR ****\r
+.equ SPIE = 7 \r
+.equ SPE = 6\r
+.equ DORD = 5\r
+.equ MSTR = 4\r
+.equ CPOL = 3\r
+.equ CPHA = 2\r
+.equ SPR1 = 1\r
+.equ SPR0 = 0\r
+\r
+; **** SPSR ****\r
+.equ SPIF = 7 \r
+.equ WCOL = 6\r
+.equ SPI2X = 0\r
+\r
+; **** I2C/TWI ****\r
+; **** I2CR ****\r
+.equ I2INT = 7 \r
+.equ I2EA = 6\r
+.equ I2STA = 5\r
+.equ I2STO = 4\r
+.equ I2WC = 3\r
+.equ ENI2C = 2\r
+.equ I2EN = 2\r
+.equ I2C_TST = 1 ; Present in core test mode only. Write Only.\r
+.equ I2IE = 0\r
+\r
+; **** I2SR ****\r
+.equ I2S7 = 7 \r
+.equ I2S6 = 6\r
+.equ I2S5 = 5\r
+.equ I2S4 = 4\r
+.equ I2S3 = 3\r
+.equ I2GCE = 0 \r
+ \r
+; **** I2AR ****\r
+.equ TWINT = 7\r
+.equ TWEA = 6\r
+.equ TWSTA = 5\r
+.equ TWSTO = 4\r
+.equ TWWC = 3\r
+.equ TWEN = 2\r
+.equ TWC_TST = 1 ; Present in core test mode only. Write Only.\r
+.equ TWIE = 0\r
+\r
+; **** TWSR ****\r
+.equ TWS7 = 7 \r
+.equ TWS6 = 6\r
+.equ TWS5 = 5\r
+.equ TWS4 = 4\r
+.equ TWS3 = 3\r
+.equ TWPS1 = 1\r
+.equ TWPS0 = 0\r
+\r
+; **** TWAR ****\r
+.equ TWA6 = 7\r
+.equ TWA5 = 6\r
+.equ TWA4 = 5\r
+.equ TWA3 = 4\r
+.equ TWA2 = 3\r
+.equ TWA1 = 2\r
+.equ TWA0 = 1\r
+.equ TWGCE = 0\r
+\r
+; **** PORT A ****\r
+; **** PORTA ****\r
+.equ PA7 = 7 \r
+.equ PA6 = 6\r
+.equ PA5 = 5\r
+.equ PA4 = 4\r
+.equ PA3 = 3\r
+.equ PA2 = 2\r
+.equ PA1 = 1\r
+.equ PA0 = 0\r
+.equ PORTA7 = 7\r
+.equ PORTA6 = 6\r
+.equ PORTA5 = 5\r
+.equ PORTA4 = 4\r
+.equ PORTA3 = 3\r
+.equ PORTA2 = 2\r
+.equ PORTA1 = 1\r
+.equ PORTA0 = 0\r
+\r
+; **** DDRA ****\r
+.equ DDA7 = 7 \r
+.equ DDA6 = 6\r
+.equ DDA5 = 5\r
+.equ DDA4 = 4\r
+.equ DDA3 = 3\r
+.equ DDA2 = 2\r
+.equ DDA1 = 1\r
+.equ DDA0 = 0\r
+\r
+; **** PINA ****\r
+.equ PINA7 = 7 \r
+.equ PINA6 = 6\r
+.equ PINA5 = 5\r
+.equ PINA4 = 4\r
+.equ PINA3 = 3\r
+.equ PINA2 = 2\r
+.equ PINA1 = 1\r
+.equ PINA0 = 0\r
+\r
+; **** PORT B ****\r
+; **** PORTB ****\r
+.equ PB7 = 7 \r
+.equ PB6 = 6\r
+.equ PB5 = 5\r
+.equ PB4 = 4\r
+.equ PB3 = 3\r
+.equ PB2 = 2\r
+.equ PB1 = 1\r
+.equ PB0 = 0\r
+.equ PORTB7 = 7\r
+.equ PORTB6 = 6\r
+.equ PORTB5 = 5\r
+.equ PORTB4 = 4\r
+.equ PORTB3 = 3\r
+.equ PORTB2 = 2\r
+.equ PORTB1 = 1\r
+.equ PORTB0 = 0\r
+\r
+; **** DDRB ****\r
+.equ DDB7 = 7 \r
+.equ DDB6 = 6\r
+.equ DDB5 = 5\r
+.equ DDB4 = 4\r
+.equ DDB3 = 3\r
+.equ DDB2 = 2\r
+.equ DDB1 = 1\r
+.equ DDB0 = 0\r
+\r
+; **** PINB ****\r
+.equ PINB7 = 7 \r
+.equ PINB6 = 6\r
+.equ PINB5 = 5\r
+.equ PINB4 = 4\r
+.equ PINB3 = 3\r
+.equ PINB2 = 2\r
+.equ PINB1 = 1\r
+.equ PINB0 = 0\r
+\r
+;**** PORTC ****\r
+.equ PC7 = 7 \r
+.equ PC6 = 6\r
+.equ PC5 = 5\r
+.equ PC4 = 4\r
+.equ PC3 = 3\r
+.equ PC2 = 2\r
+.equ PC1 = 1\r
+.equ PC0 = 0\r
+.equ PORTC7 = 7\r
+.equ PORTC6 = 6\r
+.equ PORTC5 = 5\r
+.equ PORTC4 = 4\r
+.equ PORTC3 = 3\r
+.equ PORTC2 = 2\r
+.equ PORTC1 = 1\r
+.equ PORTC0 = 0\r
+\r
+; **** DDRC ****\r
+.equ DDC7 = 7 \r
+.equ DDC6 = 6\r
+.equ DDC5 = 5\r
+.equ DDC4 = 4\r
+.equ DDC3 = 3\r
+.equ DDC2 = 2\r
+.equ DDC1 = 1\r
+.equ DDC0 = 0\r
+\r
+; **** PINC ****\r
+.equ PINC7 = 7 \r
+.equ PINC6 = 6\r
+.equ PINC5 = 5\r
+.equ PINC4 = 4\r
+.equ PINC3 = 3\r
+.equ PINC2 = 2\r
+.equ PINC1 = 1\r
+.equ PINC0 = 0\r
+\r
+;**** PORTD ****\r
+.equ PD7 = 7 \r
+.equ PD6 = 6\r
+.equ PD5 = 5\r
+.equ PD4 = 4\r
+.equ PD3 = 3\r
+.equ PD2 = 2\r
+.equ PD1 = 1\r
+.equ PD0 = 0\r
+.equ PORTD7 = 7\r
+.equ PORTD6 = 6\r
+.equ PORTD5 = 5\r
+.equ PORTD4 = 4\r
+.equ PORTD3 = 3\r
+.equ PORTD2 = 2\r
+.equ PORTD1 = 1\r
+.equ PORTD0 = 0\r
+\r
+; **** DDRD ****\r
+.equ DDD7 = 7 \r
+.equ DDD6 = 6\r
+.equ DDD5 = 5\r
+.equ DDD4 = 4\r
+.equ DDD3 = 3\r
+.equ DDD2 = 2\r
+.equ DDD1 = 1\r
+.equ DDD0 = 0\r
+\r
+; **** PIND ****\r
+.equ PIND7 = 7 \r
+.equ PIND6 = 6\r
+.equ PIND5 = 5\r
+.equ PIND4 = 4\r
+.equ PIND3 = 3\r
+.equ PIND2 = 2\r
+.equ PIND1 = 1\r
+.equ PIND0 = 0\r
+\r
+;**** PORTE ****\r
+.equ PE7 = 7\r
+.equ PE6 = 6\r
+.equ PE5 = 5\r
+.equ PE4 = 4\r
+.equ PE3 = 3\r
+.equ PE2 = 2\r
+.equ PE1 = 1\r
+.equ PE0 = 0\r
+.equ PORTE7 = 7\r
+.equ PORTE6 = 6\r
+.equ PORTE5 = 5\r
+.equ PORTE4 = 4\r
+.equ PORTE3 = 3\r
+.equ PORTE2 = 2\r
+.equ PORTE1 = 1\r
+.equ PORTE0 = 0\r
+\r
+; **** DDRE ****\r
+.equ DDE7 = 7 \r
+.equ DDE6 = 6\r
+.equ DDE5 = 5\r
+.equ DDE4 = 4\r
+.equ DDE3 = 3\r
+.equ DDE2 = 2\r
+.equ DDE1 = 1\r
+.equ DDE0 = 0\r
+\r
+; **** PINE ****\r
+.equ PINE7 = 7 \r
+.equ PINE6 = 6\r
+.equ PINE5 = 5\r
+.equ PINE4 = 4\r
+.equ PINE3 = 3\r
+.equ PINE2 = 2\r
+.equ PINE1 = 1\r
+.equ PINE0 = 0\r
+\r
+; **** PORTF ****\r
+.equ PF7 = 7 \r
+.equ PF6 = 6\r
+.equ PF5 = 5\r
+.equ PF4 = 4\r
+.equ PF3 = 3\r
+.equ PF2 = 2\r
+.equ PF1 = 1\r
+.equ PF0 = 0\r
+.equ PORTF7 = 7\r
+.equ PORTF6 = 6\r
+.equ PORTF5 = 5\r
+.equ PORTF4 = 4\r
+.equ PORTF3 = 3\r
+.equ PORTF2 = 2\r
+.equ PORTF1 = 1\r
+.equ PORTF0 = 0\r
+\r
+; **** DDRF ****\r
+.equ DDF7 = 7 \r
+.equ DDF6 = 6\r
+.equ DDF5 = 5\r
+.equ DDF4 = 4\r
+.equ DDF3 = 3\r
+.equ DDF2 = 2\r
+.equ DDF1 = 1\r
+.equ DDF0 = 0\r
+\r
+; **** PINF ****\r
+.equ PINF7 = 7 \r
+.equ PINF6 = 6\r
+.equ PINF5 = 5\r
+.equ PINF4 = 4\r
+.equ PINF3 = 3\r
+.equ PINF2 = 2\r
+.equ PINF1 = 1\r
+.equ PINF0 = 0\r
+\r
+; **** PORTG ****\r
+.equ PG4 = 4 \r
+.equ PG3 = 3\r
+.equ PG2 = 2 \r
+.equ PG1 = 1\r
+.equ PG0 = 0\r
+\r
+; **** DDRG ****\r
+.equ DDG4 = 4 \r
+.equ DDG3 = 3\r
+.equ DDG2 = 2\r
+.equ DDG1 = 1\r
+.equ DDG0 = 0\r
+\r
+; **** PING ****\r
+.equ PING4 = 4\r
+.equ PING3 = 3 \r
+.equ PING2 = 2\r
+.equ PING1 = 1\r
+.equ PING0 = 0\r
+\r
+\r
+;*****************************************************************************\r
+; CPU Register Declarations\r
+;*****************************************************************************\r
+\r
+.def XL = r26 ; X pointer low\r
+.def XH = r27 ; X pointer high\r
+.def YL = r28 ; Y pointer low\r
+.def YH = r29 ; Y pointer high\r
+.def ZL = r30 ; Z pointer low\r
+.def ZH = r31 ; Z pointer high\r
+\r
+\r
+;*****************************************************************************\r
+; Data Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ RAMEND = $10ff ; Highest internal data memory (SRAM) address.\r
+.equ EEPROMEND = $07ff ; Highest EEPROM address.\r
+ \r
+;*****************************************************************************\r
+; Program Memory Declarations\r
+;*****************************************************************************\r
+\r
+.equ FLASHEND = $7FFF ; Highest program memory (flash) address\r
+ ; (When addressed as 16 bit words)\r
+ \r
+;**** Boot Vectors ****\r
+ ; byte groups\r
+ ; /--\/--\/--\/--\ \r
+.equ SMALLBOOTSTART = 0b0111111000000000 ; ($7E00) Smallest boot block is 512W\r
+.equ SECONDBOOTSTART = 0b0111110000000000 ; ($7C00) 2'nd boot block size is 1KW\r
+.equ THIRDBOOTSTART = 0b0111100000000000 ; ($7800) Third boot block size is 2KW\r
+.equ LARGEBOOTSTART = 0b0111000000000000 ; ($7000) Largest boot block is 4KW\r
+\r
+\r
+;**** Page Size ****\r
+.equ PAGESIZE = 128 ; Number of WORDS in a page\r
+\r
+\r
+;**** Interrupt Vectors ****\r
+.equ INT0addr = $002 ; External Interrupt0 Vector Address\r
+.equ INT1addr = $004 ; External Interrupt1 Vector Address\r
+.equ INT2addr = $006 ; External Interrupt2 Vector Address\r
+.equ INT3addr = $008 ; External Interrupt3 Vector Address\r
+.equ INT4addr = $00a ; External Interrupt4 Vector Address\r
+.equ INT5addr = $00c ; External Interrupt5 Vector Address\r
+.equ INT6addr = $00e ; External Interrupt6 Vector Address\r
+.equ INT7addr = $010 ; External Interrupt7 Vector Address\r
+.equ OC2addr = $012 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr = $014 ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr = $016 ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr = $018 ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr = $01a ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr = $01c ; Overflow1 Interrupt Vector Address\r
+.equ OC0addr = $01e ; Output Compare0 Interrupt Vector Address\r
+.equ OVF0addr = $020 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr = $022 ; SPI Interrupt Vector Address\r
+.equ URXC0addr = $024 ; USART0 Receive Complete Interrupt Vector Address\r
+.equ UDRE0addr = $026 ; USART0 Data Register Empty Interrupt Vector Address\r
+.equ UTXC0addr = $028 ; USART0 Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr = $02a ; ADC Conversion Complete Handle\r
+.equ ERDYaddr = $02c ; EEPROM Write Complete Handle\r
+.equ ACIaddr = $02e ; Analog Comparator Interrupt Vector Address\r
+\r
+.equ OC1Caddr = $030 ; Output Compare1C Interrupt Vector Address\r
+.equ ICP3addr = $032 ; Input Capture3 Interrupt Vector Address\r
+.equ OC3Aaddr = $034 ; Output Compare3A Interrupt Vector Address\r
+.equ OC3Baddr = $036 ; Output Compare3B Interrupt Vector Address\r
+.equ OC3Caddr = $038 ; Output Compare3C Interrupt Vector Address\r
+.equ OVF3addr = $03A ; Overflow3 Interrupt Vector Address\r
+.equ URXC1addr = $03C ; USART1 Receive Complete Interrupt Vector Address\r
+.equ UDRE1addr = $03E ; USART1 Data Register Empty Interrupt Vector Address\r
+.equ UTXC1addr = $040 ; USART1 Transmit Complete Interrupt Vector Address\r
+.equ I2Caddr = $042 ; I2C Interrupt Vector Address\r
+.equ TWIaddr = $042 ; TWI Interrupt Vector Address\r
+.equ SPMRaddr = $044 ; Store Program Memory Ready Interrupt Vector Address\r
+\r
+\r
+;**** End of File ****\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m83def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega83\r
+;* Date :00.12.12\r
+;* Version :\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega83\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+;.device ATmega83\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRHI =$20\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ USR =$0b ; For compatibility with S8535\r
+.equ UCSRB =$0a\r
+.equ UCR =$0a ; For compatibility with S8535\r
+.equ UBRR =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+; GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+\r
+; GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+; TIMSK\r
+.equ TOIE0 =0\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+; TIFR\r
+.equ TOV0 =0\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+; SPMCR\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+.equ TWI_TST =1 ;Present in core test mode only. Write Only.\r
+.equ TWIE =0\r
+\r
+; MCUCR\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+; MCUSR\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+; TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+; SFIOR\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+; TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1\r
+.equ PWM10 =0\r
+\r
+; TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+; TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3\r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+; ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+; PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+; DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+; PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+; PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+; DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+; PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+; PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+; DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+; PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+; PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+; DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+; PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+; SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+; SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+; UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+; UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+; ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+; ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+; ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWAR\r
+.equ TWA6 =7\r
+.equ TWA5 =6\r
+.equ TWA4 =5\r
+.equ TWA3 =4\r
+.equ TWA2 =3\r
+.equ TWA1 =2\r
+.equ TWA0 =1\r
+.equ TWGCE =0\r
+\r
+; TWSR\r
+.equ TWS7 =7\r
+.equ TWS6 =6\r
+.equ TWS5 =5\r
+.equ TWS4 =4\r
+.equ TWS3 =3\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND =$1FFF\r
+.equ E2END =$1FF\r
+.equ RAMEND =$25F\r
+\r
+.equ BOOTSTART =$1E00 ;OBSOLETE!!! temporarily kept for compatibility\r
+;.equ LARGEBOOTSTART =$0C00 ;largest boot block is 2KB\r
+;.equ SMALLBOOTSTART =$0F80 ;smallest boot block is 256B\r
+.equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B\r
+.equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B\r
+.equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB\r
+.equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB\r
+.equ PAGESIZE =64 ;number of WORDS in a page\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$004 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$005 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$006 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$008 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00a ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$00b ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00c ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00d ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00e ;ADC Interrupt Vector Address\r
+.equ ERDYaddr=$00f ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$010 ;Analog Comparator Interrupt Vector Address\r
+.equ TWSIaddr=$011 ;Irq. vector address for Two-Wire Interface\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m8515def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega8515\r
+;* Date :April 16th, 2002\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :support@atmel.no\r
+;* Target MCU :ATmega8515\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega8515\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GICR =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ EMCUCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further \r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OCR0 =$31\r
+.equ SFIOR =$30 \r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$25\r
+.equ ICR1L =$24\r
+.equ WDTCR =$21\r
+.equ UCSRC =$20 ; Note! UCSRC equals UBRRH\r
+.equ UBRRH =$20 ; Note! UCSRC equals UBRRH \r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UBRR =$09 ; for AT90S8515\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ PORTE =$07\r
+.equ DDRE =$06\r
+.equ PINE =$05\r
+.equ OSCCAL =$04 ; New\r
+\r
+;***** Bit Definitions\r
+;GIMSK\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+ \r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE1 =7\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TICIE1 =3\r
+.equ TOIE0 =1\r
+.equ OCIE0 =0\r
+\r
+;TIFR\r
+.equ TOV1 =7\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ ICF1 =3\r
+.equ TOV0 =1\r
+.equ OCF0 =0\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ ASB =6 ; old\r
+.equ RWWSRE =4\r
+.equ ASRE =4 ; old\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;EMCUCR\r
+.equ SM0 =7\r
+.equ SRL2 =6\r
+.equ SRL1 =5\r
+.equ SRL0 =4\r
+.equ SRW01 =3\r
+.equ SRW00 =2\r
+.equ SRW11 =1\r
+.equ ISC2 =0\r
+\r
+;MCUCR\r
+.equ SRE =7\r
+.equ SRW =6\r
+.equ SRW10 =6 \r
+.equ SE =5\r
+.equ SM =4\r
+.equ SM1 =4 \r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUSR\r
+.equ SM2 =5 \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+ \r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ WGM00 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ WGM01 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 = 7\r
+.equ COM1A0 = 6\r
+.equ COM1B1 = 5\r
+.equ COM1B0 = 4\r
+.equ FOC1A = 3\r
+.equ FOC1B = 2\r
+.equ PWM11 = 1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 = 0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 = 1\r
+.equ WGM10 = 0\r
+\r
+;TCCR1B\r
+.equ ICNC1 = 7\r
+.equ ICES1 = 6\r
+.equ CTC11 = 4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 = 3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 = 4\r
+.equ WGM12 = 3\r
+.equ CS12 = 2\r
+.equ CS11 = 1\r
+.equ CS10 = 0\r
+\r
+\r
+;SFIOR\r
+.equ TSM =7\r
+.equ XMBK =6\r
+.equ XMM2 =5\r
+.equ XMM1 =4\r
+.equ XMM0 =3 \r
+.equ PUD =2\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDTOE =4\r
+.equ WDCE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEWEE =2\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;PORTE\r
+.equ PE2 =2\r
+.equ PE1 =1\r
+.equ PE0 =0\r
+\r
+;DDRE\r
+.equ DDE2 =2\r
+.equ DDE1 =1\r
+.equ DDE0 =0\r
+\r
+;PINE\r
+.equ PINE2 =2\r
+.equ PINE1 =1\r
+.equ PINE0 =0\r
+ \r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ PE =2\r
+.equ UPE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ AINBG =6\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$25F\r
+.equ EEPROMEND = $1FF\r
+.equ FLASHEND = $FFF\r
+ \r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b00111110000000 ;($0F80) smallest boot block is 128W\r
+.equ SECONDBOOTSTART =0b00111100000000 ;($0F00) 2'nd boot block size is 256W\r
+.equ THIRDBOOTSTART =0b00111000000000 ;($0E00) third boot block size is 512W\r
+.equ LARGEBOOTSTART =0b00110000000000 ;($0C00) largest boot block is 1KW\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =32 ;number of WORDS in a page\r
+\r
+ \r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ ICP1addr=$003 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$004 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$005 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$006 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$007 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$008 ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$009 ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00a ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00b ;UART Transmit Complete Interrupt Vector Address\r
+.equ ACIaddr =$00c ;Analog Comparator Interrupt Vector Address\r
+\r
+.equ INT2addr=$00d ;External Interrupt2 Vector Address\r
+.equ OC0addr= $00e ;Output Compare0 Interrupt Vector Address\r
+.equ ERDYaddr=$00f ; EEPROM Interrupt Vector Address\r
+.equ SPMaddr =$010 ; SPM complete Interrupt Vector Address\r
+.equ SPMRaddr =$010 ; SPM complete Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m8535def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega8535\r
+;* Date : April 16th, 2002\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :support@atmel.no\r
+;* Target MCU :ATmega8535\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega8535\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ OCR0 =$3c\r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ;new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ I2CR =$36\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ;For compatibility, \r
+.equ MCUCSR =$34 ;keep both names until further\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRH =$20 ;Note! UCSRC equals UBRRH\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTA =$1b\r
+.equ DDRA =$1a\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UCSRC =$20 ;Note! UCSRC equals UBRRH\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSRA =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ I2DR =$03\r
+.equ I2AR =$02\r
+.equ I2SR =$01\r
+.equ I2BR =$00\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+;***** Bit definitions***** \r
+;GICR\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ INT2 =5\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ INTF2 =5\r
+\r
+;TIMSK\r
+.equ TOIE0 =0\r
+.equ OCIE0 =1\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+;TIFR\r
+.equ TOV0 =0\r
+.equ OCF0 =1\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ RWWSRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;MCUCR\r
+.equ SM2 =7\r
+.equ SE =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUCSR\r
+.equ ISC2 =6\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ FOC0 =7\r
+.equ PWM0 =6 ; OBSOLETE! Use WGM00\r
+.equ WGM00 =6\r
+.equ COM01 =5\r
+.equ COM00 =4\r
+.equ CTC0 =3 ; OBSOLETE! Use WGM01\r
+.equ WGM01 =3 \r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 =1\r
+.equ WGM10 =0\r
+\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC1 =3 ; OBSOLETE! Use WGM12\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 =4\r
+.equ WGM12 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ WGM20 =6\r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ WGM21 =3 \r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;SFIOR\r
+.equ ADTS2 =7\r
+.equ ADTS1 =6\r
+.equ ADTS0 =5\r
+.equ ADHSM =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDCE =4\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTA\r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+;DDRA\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;PINA\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC7 =7\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC7 =7\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC7 =7\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ PE =2 ; old name kept for compatibilty\r
+.equ UPE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSRA\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADATE =5 \r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+;I2CR\r
+.equ I2INT =7\r
+.equ I2EA =6\r
+.equ I2STA =5\r
+.equ I2STO =4\r
+.equ I2WC =3\r
+.equ ENI2C =2\r
+.equ I2EN =2\r
+.equ I2C_TST =1 ;Present in core test mode only. Write Only.\r
+.equ I2IE =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+.equ TWI_TST =1 ;Present in core test mode only. Write Only.\r
+.equ TWIE =0\r
+\r
+;I2AR\r
+.equ I2GCE =0\r
+\r
+; TWAR\r
+.equ TWA6 =7\r
+.equ TWA5 =6\r
+.equ TWA4 =5\r
+.equ TWA3 =4\r
+.equ TWA2 =3\r
+.equ TWA1 =2\r
+.equ TWA0 =1\r
+.equ TWGCE =0\r
+\r
+; TWSR\r
+.equ TWS7 =7\r
+.equ TWS6 =6\r
+.equ TWS5 =5\r
+.equ TWS4 =4\r
+.equ TWS3 =3\r
+.equ TWS2 =2\r
+.equ TWS1 =1\r
+.equ TWS0 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$25F\r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b00111110000000 ;($0F80) smallest boot block is 128W\r
+.equ SECONDBOOTSTART =0b00111100000000 ;($0F00) 2'nd boot block size is 256W\r
+.equ THIRDBOOTSTART =0b00111000000000 ;($0E00) third boot block size is 512W\r
+.equ LARGEBOOTSTART =0b00110000000000 ;($0C00) largest boot block is 1KW\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =32 ;number of WORDS in a page\r
+.equ FLASHEND =$fff\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ;External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ;Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$004 ;Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$005 ;Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$006 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$008 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ;Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00a ;SPI Interrupt Vector Address\r
+.equ URXCaddr=$00b ;UART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00c ;UART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00d ;UART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00e ;ADC Interrupt Vector Address\r
+.equ ERDYaddr=$00f ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$010 ;Analog Comparator Interrupt Vector Address\r
+.equ TWIaddr =$011 ;Irq. vector address for Two-Wire Interface\r
+.equ I2Caddr =$011 ; Irq. vector address for Inter Intergrated Circuit interface\r
+.equ INT2addr=$012 ;External Interrupt2 Vector Address\r
+.equ OC0addr =$013 ;Output Compare0 Interrupt Vector Address\r
+.equ SPMRaddr=$014 ;Store Program Memory Ready Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"m8def.inc"\r
+;* Title :Register/Bit Definitions for the ATmega8\r
+;* Date :07.09.2001\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.no\r
+;* Target MCU :ATmega8\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATmega8\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPH =$3e\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GICR =$3b ; new name for GIMSK\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ SPMCR =$37\r
+.equ I2CR =$36\r
+.equ TWCR =$36\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34 ; For compatibility, \r
+.equ MCUCSR =$34 ; keep both names until further\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ SFIOR =$30\r
+.equ TCCR1A =$2f\r
+.equ TCCR1B =$2e\r
+.equ TCNT1H =$2d\r
+.equ TCNT1L =$2c\r
+.equ OCR1AH =$2b\r
+.equ OCR1AL =$2a\r
+.equ OCR1BH =$29\r
+.equ OCR1BL =$28\r
+.equ ICR1H =$27\r
+.equ ICR1L =$26\r
+.equ TCCR2 =$25\r
+.equ TCNT2 =$24\r
+.equ OCR2 =$23\r
+.equ ASSR =$22\r
+.equ WDTCR =$21\r
+.equ UBRRH =$20 ; Note! UCSRC equals UBRRH\r
+.equ EEARH =$1f\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ PORTC =$15\r
+.equ DDRC =$14\r
+.equ PINC =$13\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ SPDR =$0f\r
+.equ SPSR =$0e\r
+.equ SPCR =$0d\r
+.equ UDR =$0c\r
+.equ UCSRA =$0b\r
+.equ UCSRB =$0a\r
+.equ UCSRC =$20 ; Note! UCSRC equals UBRRH\r
+.equ UBRRL =$09\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+.equ I2DR =$03\r
+.equ I2AR =$02\r
+.equ I2SR =$01\r
+.equ I2BR =$00\r
+.equ TWDR =$03\r
+.equ TWAR =$02\r
+.equ TWSR =$01\r
+.equ TWBR =$00\r
+\r
+\r
+\r
+;***** Bit Definitions\r
+;GICR (former GIMSK)\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ IVSEL =1 ; interrupt vector select\r
+.equ IVCE =0 ; interrupt vector change enable\r
+\r
+;GIFR\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+\r
+;TIMSK\r
+.equ TOIE0 =0\r
+.equ TOIE1 =2\r
+.equ OCIE1B =3\r
+.equ OCIE1A =4\r
+.equ TICIE1 =5\r
+.equ TOIE2 =6\r
+.equ OCIE2 =7\r
+\r
+;TIFR\r
+.equ TOV0 =0\r
+.equ TOV1 =2\r
+.equ OCF1B =3\r
+.equ OCF1A =4\r
+.equ ICF1 =5\r
+.equ TOV2 =6\r
+.equ OCF2 =7\r
+\r
+;SPMCR\r
+.equ SPMIE =7\r
+.equ RWWSB =6\r
+.equ RWWSRE =4\r
+.equ BLBSET =3\r
+.equ PGWRT =2\r
+.equ PGERS =1\r
+.equ SPMEN =0\r
+\r
+;MCUCR\r
+.equ SE =7\r
+.equ SM2 =6\r
+.equ SM1 =5\r
+.equ SM0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;MCUCSR\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;TCCR1A\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM11 =1 ; OBSOLETE! Use WGM11\r
+.equ PWM10 =0 ; OBSOLETE! Use WGM10\r
+.equ WGM11 =1\r
+.equ WGM10 =0\r
+;TCCR1B\r
+.equ ICNC1 =7\r
+.equ ICES1 =6\r
+.equ CTC11 =4 ; OBSOLETE! Use WGM13\r
+.equ CTC10 =3 ; OBSOLETE! Use WGM12\r
+.equ WGM13 =4\r
+.equ WGM12 =3 \r
+.equ CTC1 =3 ; Obsolete - Included for backward compatibility\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;TCCR2\r
+.equ FOC2 =7\r
+.equ PWM2 =6 ; OBSOLETE! Use WGM20\r
+.equ WGM20 =6 \r
+.equ COM21 =5\r
+.equ COM20 =4\r
+.equ CTC2 =3 ; OBSOLETE! Use WGM21\r
+.equ WGM21 =3 \r
+.equ CS22 =2\r
+.equ CS21 =1\r
+.equ CS20 =0\r
+\r
+;SFIOR\r
+.equ ADHSM =4\r
+.equ ACME =3\r
+.equ PUD =2\r
+.equ PSR2 =1\r
+.equ PSR10 =0\r
+\r
+;WDTCR\r
+.equ WDCE =4\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;PORTB\r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+;DDRB\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;PINB\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;PORTC\r
+.equ PC6 =6\r
+.equ PC5 =5\r
+.equ PC4 =4\r
+.equ PC3 =3\r
+.equ PC2 =2\r
+.equ PC1 =1\r
+.equ PC0 =0\r
+\r
+;DDRC\r
+.equ DDC6 =6\r
+.equ DDC5 =5\r
+.equ DDC4 =4\r
+.equ DDC3 =3\r
+.equ DDC2 =2\r
+.equ DDC1 =1\r
+.equ DDC0 =0\r
+\r
+;PINC\r
+.equ PINC6 =6\r
+.equ PINC5 =5\r
+.equ PINC4 =4\r
+.equ PINC3 =3\r
+.equ PINC2 =2\r
+.equ PINC1 =1\r
+.equ PINC0 =0\r
+\r
+;PORTD\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+;DDRD\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+;PIND\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+;UCSRA\r
+.equ RXC =7\r
+.equ TXC =6\r
+.equ UDRE =5\r
+.equ FE =4\r
+.equ OR =3 ; old name kept for compatibilty\r
+.equ DOR =3\r
+.equ UPE =2\r
+.equ PE =2\r
+.equ U2X =1\r
+.equ MPCM =0\r
+\r
+;UCSRB\r
+.equ RXCIE =7\r
+.equ TXCIE =6\r
+.equ UDRIE =5\r
+.equ RXEN =4\r
+.equ TXEN =3\r
+.equ CHR9 =2 ; old name kept for compatibilty\r
+.equ UCSZ2 =2\r
+.equ RXB8 =1\r
+.equ TXB8 =0\r
+\r
+;UCSRC\r
+.equ URSEL =7\r
+.equ UMSEL =6\r
+.equ UPM1 =5\r
+.equ UPM0 =4\r
+.equ USBS =3\r
+.equ UCSZ1 =2\r
+.equ UCSZ0 =1\r
+.equ UCPOL =0\r
+ \r
+;SPCR\r
+.equ SPIE =7\r
+.equ SPE =6\r
+.equ DORD =5\r
+.equ MSTR =4\r
+.equ CPOL =3\r
+.equ CPHA =2\r
+.equ SPR1 =1\r
+.equ SPR0 =0\r
+\r
+;SPSR\r
+.equ SPIF =7\r
+.equ WCOL =6\r
+.equ SPI2X =0\r
+\r
+;ACSR\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIC =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+; TWCR\r
+.equ TWINT =7\r
+.equ TWEA =6\r
+.equ TWSTA =5\r
+.equ TWSTO =4\r
+.equ TWWC =3\r
+.equ TWEN =2\r
+\r
+.equ TWIE =0\r
+\r
+; TWAR\r
+.equ TWA6 =7\r
+.equ TWA5 =6\r
+.equ TWA4 =5\r
+.equ TWA3 =4\r
+.equ TWA2 =3\r
+.equ TWA1 =2\r
+.equ TWA0 =1\r
+.equ TWGCE =0\r
+\r
+; TWSR\r
+.equ TWS7 =7\r
+.equ TWS6 =6\r
+.equ TWS5 =5\r
+.equ TWS4 =4\r
+.equ TWS3 =3\r
+.equ TWPS1 =1\r
+.equ TWPS0 =0\r
+\r
+;ASSR\r
+.equ AS2 =3\r
+.equ TCN2UB =2\r
+.equ OCR2UB =1\r
+.equ TCR2UB =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$45F\r
+.equ FLASHEND =$FFF\r
+\r
+ ; byte groups\r
+ ; /\/--\/--\/--\ \r
+.equ SMALLBOOTSTART =0b00111110000000 ;($0F80) smallest boot block is 256\r
+.equ SECONDBOOTSTART =0b00111100000000 ;($0F00) 2'nd boot block size is 512\r
+.equ THIRDBOOTSTART =0b00111000000000 ;($0E00) third boot block size is 1K\r
+.equ LARGEBOOTSTART =0b00110000000000 ;($0C00) largest boot block is 2K\r
+.equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility\r
+.equ PAGESIZE =32 ;number of WORDS in a page\r
+\r
+.equ INT0addr=$001 ; External Interrupt0 Vector Address\r
+.equ INT1addr=$002 ; External Interrupt1 Vector Address\r
+.equ OC2addr =$003 ; Output Compare2 Interrupt Vector Address\r
+.equ OVF2addr=$004 ; Overflow2 Interrupt Vector Address\r
+.equ ICP1addr=$005 ; Input Capture1 Interrupt Vector Address\r
+.equ OC1Aaddr=$006 ; Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr=$007 ; Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr=$008 ; Overflow1 Interrupt Vector Address\r
+.equ OVF0addr=$009 ; Overflow0 Interrupt Vector Address\r
+.equ SPIaddr =$00a ; SPI Interrupt Vector Address\r
+.equ URXCaddr=$00b ; USART Receive Complete Interrupt Vector Address\r
+.equ UDREaddr=$00c ; USART Data Register Empty Interrupt Vector Address\r
+.equ UTXCaddr=$00d ; USART Transmit Complete Interrupt Vector Address\r
+.equ ADCCaddr=$00e ; ADC Interrupt Vector Address\r
+.equ ERDYaddr=$00f ; EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$010 ; Analog Comparator Interrupt Vector Address\r
+.equ TWIaddr =$011 ; Irq. vector address for Two-Wire Interface\r
+.equ SPMaddr =$012 ; SPM complete Interrupt Vector Address\r
+.equ SPMRaddr =$012 ; SPM complete Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tn11def.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny11\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :ATtiny11\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the two registers forming the data pointers Z have been \r
+;* assigned names ZL - ZH. \r
+;*\r
+;* The Register names are represented by their hexadecimal addresses.\r
+;*\r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;*\r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"\r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;*\r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB2)+(1<<PB1) ;set PB2 and PB1 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+\r
+\r
+;***** Specify Device\r
+.device ATtiny11\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ WDTCR =$21\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ ACSR =$08\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT0 =6\r
+.equ PCIE =5\r
+\r
+.equ INTF0 =6\r
+.equ PCIF =5\r
+\r
+.equ TOIE0 =1\r
+\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.def ZL =R30\r
+.def ZH =R31\r
+\r
+.equ FLASHEND=$1FF\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ PCINTaddr=$002 ;Pin change Interrupt Vector Address\r
+.equ OVF0addr=$003 ;Overflow0 Interrupt Vector Address\r
+.equ ACIaddr =$004 ;Analog Comparator Interrupt Vector Address\r
+\r
--- /dev/null
+\r
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tn12.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny12\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :ATtiny12\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the two registers forming the data pointer Z have been \r
+;* assigned names ZL - ZH. \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny12\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ ACSR =$08\r
+\r
+;***** Bit Definitions\r
+.equ INT0 =6\r
+.equ PCIE =5\r
+\r
+.equ INTF0 =6\r
+.equ PCIF =5\r
+\r
+.equ TOIE0 =1\r
+\r
+.equ TOV0 =1\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ PUD =6\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ WDDE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ CAL7 =7\r
+.equ CAL6 =6\r
+.equ CAL5 =5\r
+.equ CAL4 =4\r
+.equ CAL3 =3\r
+.equ CAL2 =2\r
+.equ CAL1 =1\r
+.equ CAL0 =0\r
+\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ ACD =7\r
+.equ AINBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ FLASHEND=$1FF\r
+.equ E2END =$3F\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ PCINTaddr=$002 ;Pin change Interrupt Vector Address\r
+.equ OVF0addr=$003 ;Overflow0 Interrupt Vector Address\r
+.equ ERDYaddr =$004 ;EEPROM Interrupt Vector Address\r
+.equ ACIaddr =$005 ;Analog Comparator Interrupt Vector Address\r
+\r
--- /dev/null
+; Last change: TF 8 Sep 99 8:18 pm\r
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;*\r
+;* Number : AVR000\r
+;* File Name : "T15def.inc"\r
+;* Title : Register/Bit Definitions for the ATtiny15\r
+;* Date : 1999.09.08\r
+;* Version : 1.00\r
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax : +47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-Mail : avr@atmel.com\r
+;* Target MCU : ATtiny15\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;*\r
+;* The Register names are represented by their hexadecimal addresses.\r
+;*\r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;*\r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"\r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;*\r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny15\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3F\r
+.equ SPL =$3D ; ICE only !!!!!!\r
+.equ GIMSK =$3B\r
+.equ GIFR =$3A\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ TCCR1 =$30\r
+.equ TCNT1 =$2F\r
+.equ OCR1A =$2E\r
+.equ OCR1B =$2D\r
+.equ SFIOR =$2C\r
+.equ WDTCR =$21\r
+.equ EEAR =$1E\r
+.equ EEDR =$1D\r
+.equ EECR =$1C\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+\r
+;***** Bit Definitions\r
+\r
+; GIMSK\r
+.equ INT0 =6\r
+.equ PCIE =5\r
+\r
+; GIFR\r
+.equ INTF0 =6\r
+.equ PCIF =5\r
+\r
+; TIMSK\r
+.equ OCIE1 =6\r
+.equ TOIE1 =2\r
+.equ TOIE0 =1\r
+\r
+; TIFR\r
+.equ OCF1 =6\r
+.equ TOV1 =2\r
+.equ TOV0 =1\r
+\r
+; MCUCR\r
+\r
+.equ PUD =6\r
+.equ SE =5\r
+.equ SM =4\r
+.equ SM1 =4\r
+.equ SM0 =3\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+; MCUSR\r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+; TCCR0\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+; TCCR1\r
+.equ CTC1 =7\r
+.equ PWM1 =6\r
+.equ COM1A1 =5\r
+.equ COM1A0 =4\r
+.equ CS13 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+; WDTCR\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+; EECR\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+; PORTB\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+; DDRB\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+; PINB\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+; ACSR\r
+.equ ACD =7\r
+.equ AINBG6 =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+; ADMUX\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;ADCSR\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+;SFIOR\r
+.equ FOC1A =2\r
+.equ PSR1 =1\r
+.equ PSR0 =0\r
+\r
+.equ RAMEND =0 ; Last On-Chip SRAM Location\r
+.equ XRAMEND =0 ; Last External RAM Location\r
+.equ E2END =3F ; Last EEPROM Location\r
+.equ FLASHEND=1FF ; Last FLASH Location\r
+\r
+.equ INT0addr=$001 ; External Interrupt0 Vector Address\r
+.equ PCaddr =$002 ; Pin Change Interrupt Vector Address\r
+.equ T1CPaddr=$003 ; Timer1 Compare Interrupt Vector Address\r
+.equ T1OVaddr=$004 ; Timer1 Overflow Interrupt Vector Address\r
+.equ T0OVaddr=$005 ; Timer0 Overflow Interrupt Vector Address\r
+.equ ERDYaddr=$006 ; EEPROM Ready Interrupt Vector Address\r
+.equ ACaddr =$007 ; Analog Comparator Interrupt Vector Address\r
+.equ ADCaddr =$008 ; AD Converter Interrupt Vector Address\r
+\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tn22def.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny22\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-Mail :avr@atmel.com\r
+;* Target MCU :ATtiny22\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* \r
+;* The Register names are represented by their hexadecimal addresses.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny22\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ SPL =$3d\r
+.equ GIMSK =$3b\r
+.equ GIFR =$3a\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ WDTCR =$21\r
+.equ EEAR =$1e\r
+.equ EEARL =$1e\r
+.equ EEDR =$1d\r
+.equ EECR =$1c\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+\r
+;***** Bit Definitions\r
+\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT0 =6\r
+.equ INTF0 =6\r
+\r
+.equ TOIE0 =1\r
+.equ TOV0 =1\r
+\r
+.equ SE =5\r
+.equ SM =4\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF ;Last On-Chip SRAM Location\r
+.equ XRAMEND =$DF\r
+.equ E2END =$7F\r
+.equ FLASHEND=$3FF\r
+\r
+\r
+.equ INT0addr=$001 ;External Interrupt0 Vector Address\r
+.equ OVF0addr=$002 ;Overflow0 Interrupt Vector Address\r
+\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tiny26def.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny26\r
+;* Date :April 16th, 2002\r
+;* Version :1.00\r
+;* Support telephone :+47 72 88 87 20 (ATMEL Norway)\r
+;* Support fax :+47 72 88 87 18 (ATMEL Norway)\r
+;* Support E-mail :support@atmel.no\r
+;* Target MCU :ATtiny26\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register \r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the six registers forming the three data pointers X, Y and\r
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal \r
+;* SRAM is also defined \r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny26\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3F\r
+.equ SP =$3D\r
+.equ GIMSK =$3B\r
+.equ GIFR =$3A\r
+.equ TIMSK =$39\r
+.equ TIFR =$38\r
+.equ MCUCR =$35\r
+.equ MCUSR =$34\r
+.equ TCCR0 =$33\r
+.equ TCNT0 =$32\r
+.equ OSCCAL =$31\r
+.equ TCCR1A =$30\r
+.equ TCCR1B =$2F\r
+.equ TCNT1 =$2E\r
+.equ OCR1A =$2D\r
+.equ OCR1B =$2C\r
+.equ OCR1C =$2B\r
+.equ PLLCSR =$29\r
+.equ WDTCR =$21\r
+.equ EEAR =$1E\r
+.equ EEDR =$1D\r
+.equ EECR =$1C\r
+.equ PORTA =$1B\r
+.equ DDRA =$1A\r
+.equ PINA =$19\r
+.equ PORTB =$18\r
+.equ DDRB =$17\r
+.equ PINB =$16\r
+.equ USIDR =$0F\r
+.equ USISR =$0E\r
+.equ USICR =$0D\r
+.equ ACSR =$08\r
+.equ ADMUX =$07\r
+.equ ADCSR =$06\r
+.equ ADCH =$05\r
+.equ ADCL =$04\r
+\r
+;***** Bit Definitions\r
+;***** GIMSK *****\r
+.equ INT0 =6\r
+.equ PCIE1 =5\r
+.equ PCIE0 =4\r
+\r
+;***** GIFR ******\r
+.equ INTF0 =6\r
+.equ PCIF =5\r
+\r
+;***** TIMSK *****\r
+.equ OCIE1A =6\r
+.equ OCIE1B =5\r
+.equ TOIE1 =2\r
+.equ TOIE0 =1\r
+\r
+;***** TIFR ******\r
+.equ OCF1A =6\r
+.equ OCF1B =5\r
+.equ TOV1 =2\r
+.equ TOV0 =1\r
+\r
+;***** MCUCR ***** \r
+.equ PUD =6\r
+.equ SE =5\r
+.equ SM1 =4\r
+.equ SM0 =3\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+;***** MCUSR ***** \r
+.equ WDRF =3\r
+.equ BORF =2\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+;***** TCCR0 *****\r
+.equ PSR0 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+;***** OSCCAL ****\r
+.equ OSCCAL4 =4\r
+.equ OSCCAL3 =3\r
+.equ OSCCAL2 =2\r
+.equ OSCCAL1 =1\r
+.equ OSCCAL0 =0\r
+\r
+;***** TCCR1A ****\r
+.equ COM1A1 =7\r
+.equ COM1A0 =6\r
+.equ COM1B1 =5\r
+.equ COM1B0 =4\r
+.equ FOC1A =3\r
+.equ FOC1B =2\r
+.equ PWM1A =1\r
+.equ PWM1B =0\r
+\r
+;***** TCCR1B **** \r
+.equ CTC1 =7\r
+.equ PSR1 =6\r
+.equ CS13 =3\r
+.equ CS12 =2\r
+.equ CS11 =1\r
+.equ CS10 =0\r
+\r
+;***** PLLCSR ****\r
+.equ PCKE =2\r
+.equ PLLE =1\r
+.equ PLOCK =0\r
+\r
+;***** WDTCR *****\r
+.equ WDCE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+;***** EEAR ******\r
+.equ EEAR6 =6\r
+.equ EEAR5 =5\r
+.equ EEAR4 =4\r
+.equ EEAR3 =3\r
+.equ EEAR2 =2\r
+.equ EEAR1 =1\r
+.equ EEAR0 =0\r
+\r
+;***** EECR ******\r
+.equ EERIE =3\r
+.equ EEMWE =2\r
+.equ EEWE =1\r
+.equ EERE =0\r
+\r
+;***** PORTA ***** \r
+.equ PA7 =7\r
+.equ PA6 =6\r
+.equ PA5 =5\r
+.equ PA4 =4\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+.equ PORTA7 =7\r
+.equ PORTA6 =6\r
+.equ PORTA5 =5\r
+.equ PORTA4 =4\r
+.equ PORTA3 =3\r
+.equ PORTA2 =2\r
+.equ PORTA1 =1\r
+.equ PORTA0 =0\r
+\r
+;***** DDRA ******\r
+.equ DDA7 =7\r
+.equ DDA6 =6\r
+.equ DDA5 =5\r
+.equ DDA4 =4\r
+.equ DDA3 =3\r
+.equ DDA2 =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+;***** PINA ******\r
+.equ PINA7 =7\r
+.equ PINA6 =6\r
+.equ PINA5 =5\r
+.equ PINA4 =4\r
+.equ PINA3 =3\r
+.equ PINA2 =2\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+;***** PORTB ***** \r
+.equ PB7 =7\r
+.equ PB6 =6\r
+.equ PB5 =5\r
+.equ PB4 =4\r
+.equ PB3 =3\r
+.equ PB2 =2\r
+.equ PB1 =1\r
+.equ PB0 =0\r
+\r
+.equ PORTB7 =7\r
+.equ PORTB6 =6\r
+.equ PORTB5 =5\r
+.equ PORTB4 =4\r
+.equ PORTB3 =3\r
+.equ PORTB2 =2\r
+.equ PORTB1 =1\r
+.equ PORTB0 =0\r
+\r
+;***** DDRB ******\r
+.equ DDB7 =7\r
+.equ DDB6 =6\r
+.equ DDB5 =5\r
+.equ DDB4 =4\r
+.equ DDB3 =3\r
+.equ DDB2 =2\r
+.equ DDB1 =1\r
+.equ DDB0 =0\r
+\r
+;***** PINB ******\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+;***** USISR *****\r
+.equ USISIF =7\r
+.equ USIOIF =6\r
+.equ USIPF =5\r
+.equ USIDC =4\r
+.equ USICNT3 =3\r
+.equ USICNT2 =2\r
+.equ USICNT1 =1\r
+.equ USICNT0 =0\r
+\r
+;***** USICR *****\r
+.equ USISIE =7\r
+.equ USIOIE =6\r
+.equ USIWM1 =5\r
+.equ USIWM0 =4\r
+.equ USICS1 =3\r
+.equ USICS0 =2\r
+.equ USICLK =1\r
+.equ USITC =0\r
+\r
+;***** ACSR ******\r
+.equ ACD =7\r
+.equ ACBG =6\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACME =2\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+;***** ADMUX *****\r
+.equ REFS1 =7\r
+.equ REFS0 =6\r
+.equ ADLAR =5\r
+.equ MUX4 =4\r
+.equ MUX3 =3\r
+.equ MUX2 =2\r
+.equ MUX1 =1\r
+.equ MUX0 =0\r
+\r
+;***** ADCSR *****\r
+.equ ADEN =7\r
+.equ ADSC =6\r
+.equ ADFR =5\r
+.equ ADIF =4\r
+.equ ADIE =3\r
+.equ ADPS2 =2\r
+.equ ADPS1 =1\r
+.equ ADPS0 =0\r
+\r
+.def XL =r26\r
+.def XH =r27\r
+.def YL =r28\r
+.def YH =r29\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+.equ RAMEND =$DF\r
+\r
+.equ INT0addr =$001 ;External Interrupt0 Vector Address\r
+.equ IOPINSaddr =$002 ;Pin change interrupt\r
+.equ OC1Aaddr =$003 ;Output Compare1A Interrupt Vector Address\r
+.equ OC1Baddr =$004 ;Output Compare1B Interrupt Vector Address\r
+.equ OVF1addr =$005 ;Overflow1 Interrupt Vector Address\r
+.equ OVF0addr =$006 ;Overflow0 Interrupt Vector Address\r
+.equ USI_STARTaddr =$007 ;Universal Seria Bus Start Interrupt Address\r
+.equ USI_OVFaddr =$008 ;Universal Seria Bus Overflow Interrupt Address\r
+.equ ERDYaddr =$009 ;EEPROM Ready Interrupt Vector Address\r
+.equ ACIaddr =$00A ;Analog Comparator Interrupt Vector Address\r
+.equ ADCCaddr =$00B ;ADC conversion complete Interrupt Vector Address\r
--- /dev/null
+;***************************************************************************\r
+;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y\r
+;* \r
+;* Number :AVR000\r
+;* File Name :"tn28def.inc"\r
+;* Title :Register/Bit Definitions for the ATtiny28\r
+;* Date :99.01.28\r
+;* Version :1.30\r
+;* Support telephone :+47 72 88 43 88 (ATMEL Norway)\r
+;* Support fax :+47 72 88 43 99 (ATMEL Norway)\r
+;* Support E-mail :avr@atmel.com\r
+;* Target MCU :ATtiny28\r
+;*\r
+;* DESCRIPTION\r
+;* When including this file in the assembly program file, all I/O register\r
+;* names and I/O register bit names appearing in the data book can be used.\r
+;* In addition, the two registers forming the data pointers Z have been \r
+;* assigned names ZL - ZH. \r
+;*\r
+;*\r
+;* The Register names are represented by their hexadecimal address.\r
+;* \r
+;* The Register Bit names are represented by their bit number (0-7).\r
+;* \r
+;* Please observe the difference in using the bit names with instructions\r
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" \r
+;* (skip if bit in register set/cleared). The following example illustrates\r
+;* this:\r
+;* \r
+;* in r16,PORTB ;read PORTB latch\r
+;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)\r
+;* out PORTB,r16 ;output to PORTB\r
+;*\r
+;* in r16,TIFR ;read the Timer Interrupt Flag Register\r
+;* sbrc r16,TOV0 ;test the overflow flag (use bit#)\r
+;* rjmp TOV0_is_set ;jump if set\r
+;* ... ;otherwise do something else\r
+;***************************************************************************\r
+\r
+;***** Specify Device\r
+.device ATtiny28\r
+\r
+;***** I/O Register Definitions\r
+.equ SREG =$3f\r
+.equ PORTA =$1b\r
+.equ PACR =$1a\r
+.equ PINA =$19\r
+.equ PINB =$16\r
+.equ PORTD =$12\r
+.equ DDRD =$11\r
+.equ PIND =$10\r
+.equ ACSR =$08\r
+.equ MCUCS =$07\r
+.equ ICR =$06\r
+.equ IFR =$05\r
+.equ TCCR0 =$04\r
+.equ TCNT0 =$03\r
+.equ MODCR =$02\r
+.equ WDTCR =$01\r
+.equ OSCCAL =$00\r
+\r
+\r
+;***** Bit Definitions\r
+.equ PA3 =3\r
+.equ PA2 =2\r
+.equ PA1 =1\r
+.equ PA0 =0\r
+\r
+.equ DDA3 =3\r
+.equ PA2HC =2\r
+.equ DDA1 =1\r
+.equ DDA0 =0\r
+\r
+.equ PINA3 =3\r
+.equ PINA1 =1\r
+.equ PINA0 =0\r
+\r
+.equ PINB7 =7\r
+.equ PINB6 =6\r
+.equ PINB5 =5\r
+.equ PINB4 =4\r
+.equ PINB3 =3\r
+.equ PINB2 =2\r
+.equ PINB1 =1\r
+.equ PINB0 =0\r
+\r
+.equ PD7 =7\r
+.equ PD6 =6\r
+.equ PD5 =5\r
+.equ PD4 =4\r
+.equ PD3 =3\r
+.equ PD2 =2\r
+.equ PD1 =1\r
+.equ PD0 =0\r
+\r
+.equ DDD7 =7\r
+.equ DDD6 =6\r
+.equ DDD5 =5\r
+.equ DDD4 =4\r
+.equ DDD3 =3\r
+.equ DDD2 =2\r
+.equ DDD1 =1\r
+.equ DDD0 =0\r
+\r
+.equ PIND7 =7\r
+.equ PIND6 =6\r
+.equ PIND5 =5\r
+.equ PIND4 =4\r
+.equ PIND3 =3\r
+.equ PIND2 =2\r
+.equ PIND1 =1\r
+.equ PIND0 =0\r
+\r
+.equ ACD =7\r
+.equ ACO =5\r
+.equ ACI =4\r
+.equ ACIE =3\r
+.equ ACIS1 =1\r
+.equ ACIS0 =0\r
+\r
+.equ PLUPB =7\r
+.equ SE =5\r
+.equ SM =4\r
+.equ WDRF =3\r
+.equ EXTRF =1\r
+.equ PORF =0\r
+\r
+.equ INT1 =7\r
+.equ INT0 =6\r
+.equ LLIE =5\r
+.equ TOIE0 =4\r
+.equ ISC11 =3\r
+.equ ISC10 =2\r
+.equ ISC01 =1\r
+.equ ISC00 =0\r
+\r
+.equ INTF1 =7\r
+.equ INTF0 =6\r
+.equ TOV0 =4\r
+\r
+.equ FOV0 =7\r
+.equ OOM01 =4\r
+.equ OOM00 =3\r
+.equ CS02 =2\r
+.equ CS01 =1\r
+.equ CS00 =0\r
+\r
+.equ WDTOE =4\r
+.equ WDE =3\r
+.equ WDP2 =2\r
+.equ WDP1 =1\r
+.equ WDP0 =0\r
+\r
+.equ ONTIM4 =7\r
+.equ ONTIM3 =6\r
+.equ ONTIM2 =5\r
+.equ ONTIM1 =4\r
+.equ ONTIM0 =3\r
+.equ MCONF2 =2\r
+.equ MCONF1 =1\r
+.equ MCONF0 =0\r
+\r
+.equ CAL7 =7\r
+.equ CAL6 =6\r
+.equ CAL5 =5\r
+.equ CAL4 =4\r
+.equ CAL3 =3\r
+.equ CAL2 =2\r
+.equ CAL1 =1\r
+.equ CAL0 =0\r
+\r
+.def ZL =r30\r
+.def ZH =r31\r
+\r
+\r
+.equ FLASHEND = 0x07FF\r
+.equ RAMEND = 0x03FF\r
+\r
+.equ INT0addr =$001 ;External Interrupt0 Vector Address\r
+.equ INT1addr =$002 ;External Interrupt1 Vector Address\r
+.equ LLINTaddr=$003 ;Low level Interrupt Vector Address\r
+.equ OVF0addr =$004 ;Overflow0 Interrupt Vector Address\r
+.equ ACIaddr =$005 ;Analog Comparator Interrupt Vector Address\r
+\r
projects / my-code / atmel.git / commitdiff