From: hackbard <hackbard>
Date: Sat, 6 Dec 2003 01:15:10 +0000 (+0000)
Subject: include files added (all devices)
X-Git-Url: https://hackdaworld.org/gitweb/?p=my-code%2Fatmel.git;a=commitdiff_plain;h=e2b240151eadc5d18f060ffdfd364405b1ca2e56

include files added (all devices)
---

diff --git a/include/1200def.inc b/include/1200def.inc
new file mode 100644
index 0000000..b21185f
--- /dev/null
+++ b/include/1200def.inc
@@ -0,0 +1,152 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"1200def.inc"
+;* Title		:Register/Bit Definitions for the AT90S1200
+;* Date	 		:99.01.28
+;* Version		:1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-Mail	:avr@atmel.com
+;* Target MCU		:AT90S1200
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* 
+;* The Register names are represented by their hexadecimal addresses.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S1200
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	GIMSK	=$3b
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	ACSR	=$08
+
+;***** Bit Definitions
+
+.equ	INT0	=6
+
+.equ	TOIE0	=1
+
+.equ	TOV0	=1
+
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+.equ	ACD	=7
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.equ	XRAMEND =$0
+.equ	E2END	=$3F
+.equ	FLASHEND=$1FF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	OVF0addr=$002	;Overflow0 Interrupt Vector Address
+.equ	ACIaddr =$003	;Analog Comparator Interrupt Vector Address
+
+.def	ZL	=r30
+.def	ZH	=r31
diff --git a/include/2313def.inc b/include/2313def.inc
new file mode 100644
index 0000000..577d6c6
--- /dev/null
+++ b/include/2313def.inc
@@ -0,0 +1,232 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"2313def.inc"
+;* Title		:Register/Bit Definitions for the AT90S2313
+;* Date	 		:99.01.28
+;* Version		:1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-Mail	:avr@atmel.com
+;* Target MCU		:AT90S2313
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* 
+;* The Register names are represented by their hexadecimal addresses.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S2313
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPL	=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	ICR1H	=$25
+.equ	ICR1L	=$24
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	UDR	=$0c
+.equ	USR	=$0b
+.equ	UCR	=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+
+
+;***** Bit Definitions
+.equ	SP7	=7
+.equ	SP6	=6
+.equ	SP5	=5
+.equ	SP4	=4
+.equ	SP3	=3
+.equ	SP2	=2
+.equ	SP1	=1
+.equ	SP0	=0
+
+.equ	INT1	=7
+.equ	INT0	=6
+
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	TICIE	=3
+.equ	TOIE0	=1
+
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	ICF1	=3
+.equ	TOV0	=1
+
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3
+
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+.equ	ACD	=7
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ    RAMEND  =$DF    ;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$7F
+.equ	FLASHEND=$3FF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1addr =$004	;Output Compare1 Interrupt Vector Address
+.equ	OVF1addr=$005	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$006	;Overflow0 Interrupt Vector Address
+.equ	URXCaddr=$007	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$008	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$009	;UART Transmit Complete Interrupt Vector Address
+.equ	ACIaddr =$00a	;Analog Comparator Interrupt Vector Address
+
diff --git a/include/2323def.inc b/include/2323def.inc
new file mode 100644
index 0000000..2d24d73
--- /dev/null
+++ b/include/2323def.inc
@@ -0,0 +1,123 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"2323def.inc"
+;* Title		:Register/Bit Definitions for the AT90S2323
+;* Date	 		:99.01.28
+;* Version		:1.30
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax		:+47 72 88 87 18 (ATMEL Norway)
+;* Support E-Mail	:avr@atmel.com
+;* Target MCU		:AT90S2323
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* 
+;* The Register names are represented by their hexadecimal addresses.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S2323
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPL	=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+
+;***** Bit Definitions
+
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT0	=6
+.equ	INTF0	=6
+
+.equ	TOIE0	=1
+.equ	TOV0	=1
+
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ    RAMEND  =$DF    ;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$7F
+.equ	FLASHEND=$3FF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	OVF0addr=$002	;Overflow0 Interrupt Vector Address
+
diff --git a/include/2333def.inc b/include/2333def.inc
new file mode 100644
index 0000000..9c07466
--- /dev/null
+++ b/include/2333def.inc
@@ -0,0 +1,292 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"2333def.inc"
+;* Title		:Register/Bit Definitions for the AT90S2333
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	:avr@atmel.com
+;* Target MCU		:AT90S2333
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***** Specify Device
+.device AT90S2333
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SP		=$3d
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1H	=$2b
+.equ	OCR1L	=$2a
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	UCSRA 	=$0b
+.equ	UCSRB 	=$0a
+.equ	UBRR	=$09
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ	UBRRH	=$03
+
+
+;***** Bit Definitions
+.equ	WDRF	=3
+.equ	BORF	=2
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT1	=7
+.equ	INT0	=6
+
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+
+.equ    TOIE1   =7
+.equ    OCIE1   =6
+.equ    TICIE1  =3
+.equ    TOIE0   =1
+
+.equ    TOV1    =7
+.equ    OCF1    =6
+.equ    ICF1    =3
+.equ    TOV0    =1
+
+.equ    SE      =5
+.equ    SM      =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	COM11	=7
+.equ	COM10	=6
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+.equ	WDTOE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+.equ    MPCM    =0
+
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+.equ	ACD		=7
+.equ	AINBG 	=6
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.equ	ADCBG	=6
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND  =$DF	;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$7F
+.equ	FLASHEND=$3FF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$004	;Output Compare1A Interrupt Vector Address
+.equ	OVF1addr=$005	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$006	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$007	;SPI Interrupt Vector Address
+.equ	URXCaddr=$008	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$009	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00a	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr =$00b	;ADC Interrupt Vector Address
+.equ	ERDYaddr =$00c	;EEPROM Interrupt Vector Address
+.equ	ACIaddr  =$00d	;Analog Comparator Interrupt Vector Address
diff --git a/include/2343def.inc b/include/2343def.inc
new file mode 100644
index 0000000..8d8d96e
--- /dev/null
+++ b/include/2343def.inc
@@ -0,0 +1,123 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"2343def.inc"
+;* Title		:Register/Bit Definitions for the AT90S2343
+;* Date	 		:99.01.28
+;* Version		:1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-Mail	:avr@atmel.com
+;* Target MCU		:AT90S2343
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* 
+;* The Register names are represented by their hexadecimal addresses.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S2343
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPL	=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+
+;***** Bit Definitions
+
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT0	=6
+.equ	INTF0	=6
+
+.equ	TOIE0	=1
+.equ	TOV0	=1
+
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ    RAMEND  =$DF    ;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$7F
+.equ	FLASHEND=$3FF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	OVF0addr=$002	;Overflow0 Interrupt Vector Address
+
diff --git a/include/4414def.inc b/include/4414def.inc
new file mode 100644
index 0000000..0c09a99
--- /dev/null
+++ b/include/4414def.inc
@@ -0,0 +1,314 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"4414def.inc"
+;* Title				:Register/Bit Definitions for the AT90S4414
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.com
+;* Target MCU			:AT90S4414
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S4414
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$25
+.equ	ICR1L	=$24
+.equ	WDTCR	=$21
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	USR		=$0b
+.equ	UCR		=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+
+
+;***** Bit Definitions
+.equ	INT1	=7
+.equ	INT0	=6
+
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ	TICIE1	=3
+.equ	TOIE0	=1
+
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	ICF1	=3
+.equ	TOV0	=1
+
+.equ	SRE	=7
+.equ	SRW	=6
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+.equ	WDTOE	=4
+.equ	WDDE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PA7		=7
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PC7		=7
+.equ	PC6		=6
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+.equ	ACD		=7
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND  =$15F	;Last On-Chip SRAM Location
+.equ	XRAMEND =$FFFF
+.equ	E2END	=$FF
+.equ	FLASHEND=$7FF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$004	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$005	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$006	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$007	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$008	;SPI Interrupt Vector Address
+.equ	URXCaddr=$009	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00a	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00b	;UART Transmit Complete Interrupt Vector Address
+.equ	ACIaddr =$00c	;Analog Comparator Interrupt Vector Address
diff --git a/include/4433def.inc b/include/4433def.inc
new file mode 100644
index 0000000..6d3a1bc
--- /dev/null
+++ b/include/4433def.inc
@@ -0,0 +1,293 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"4433def.inc"
+;* Title		:Register/Bit Definitions for the AT90S4433
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	:avr@atmel.com
+;* Target MCU		:AT90S4433
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***** Specify Device
+.device AT90S4433
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SP	=$3d
+.equ	SPL	=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1H	=$2b
+.equ	OCR1L	=$2a
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	=$0c
+.equ	UCSRA 	=$0b
+.equ	UCSRB 	=$0a
+.equ	UBRR	=$09
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ	UBRRH	=$03
+
+
+;***** Bit Definitions
+
+.equ	WDRF	=3
+.equ	BORF	=2
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT1	=7
+.equ	INT0	=6
+
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+
+.equ    TOIE1   =7
+.equ    OCIE1   =6
+.equ    TICIE1  =3
+.equ    TOIE0   =1
+
+.equ    TOV1    =7
+.equ    OCF1    =6
+.equ    ICF1    =3
+.equ    TOV0    =1
+
+.equ    SE      =5
+.equ    SM      =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	COM11	=7
+.equ	COM10	=6
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3
+.equ    MPCM    =0
+
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+.equ	ACD	=7
+.equ	AINBG 	=6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.equ	ADCBG	=6
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND  =$DF	;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$FF
+.equ	FLASHEND=$7FF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$004	;Output Compare1A Interrupt Vector Address
+.equ	OVF1addr=$005	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$006	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$007	;SPI Interrupt Vector Address
+.equ	URXCaddr=$008	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$009	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00a	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr =$00b	;ADC Interrupt Vector Address
+.equ	ERDYaddr =$00c	;EEPROM Interrupt Vector Address
+.equ	ACIaddr  =$00d	;Analog Comparator Interrupt Vector Address
diff --git a/include/4434def.inc b/include/4434def.inc
new file mode 100644
index 0000000..1506913
--- /dev/null
+++ b/include/4434def.inc
@@ -0,0 +1,391 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"4434def.inc"
+;* Title				:Register/Bit Definitions for the AT90S4434
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.com
+;* Target MCU			:AT90S4434
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S4434
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	USR		=$0b
+.equ	UCR		=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+
+;***** Bit Definitions
+
+;MCUSR
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+;TIMSK
+.equ	OCIE2	=7
+.equ	TOIE2	=6
+.equ	TICIE1	=5
+.equ	OCIE1A	=4
+.equ	OCIE1B	=3
+.equ	TOIE1	=2
+.equ	TOIE0	=0
+
+;TIFR
+.equ	OCF2	=7
+.equ	TOV2	=6
+.equ	ICF1	=5
+.equ	OCF1A	=4
+.equ	OCF1B	=3
+.equ	TOV1	=2
+.equ	TOV0	=0
+
+;MCUCR
+.equ	SE	=6
+.equ	SM1	=5
+.equ	SM0	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	PWM2	=6
+.equ	COM21	=5
+.equ	COM20	=4
+.equ	CTC2	=3
+.equ	CS22	=2
+.equ	CS21	=1
+.equ	CS20	=0
+
+;ASSR
+.equ	AS2		=3
+.equ	TCN2UB	=2
+.equ	OCR2UB	=1
+.equ	TCR2UB	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ	EERIE	=3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7		=7
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7		=7
+.equ	PC6		=6
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;SPCR
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+;USR
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+
+;UCR
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;ACSR
+.equ	ACD		=7
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ	MUX2	=2
+.equ	MUX1	=1
+.equ	MUX0	=0
+
+;ADCSR
+.equ	ADEN	=7
+.equ	ADSC	=6
+.equ	ADFR	=5
+.equ	ADIF	=4
+.equ	ADIE	=3
+.equ	ADPS2	=2
+.equ	ADPS1	=1
+.equ	ADPS0	=0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND  =$15F	;Last On-Chip SRAM location
+.equ	XRAMEND =$15F
+.equ	E2END	=$FF
+.equ	FLASHEND=$7FF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	OC2addr =$003	;Timer2 compare match Vector Address
+.equ	OVF2addr=$004	;Timer2 overflow Vector Address
+.equ	ICP1addr=$005	;Timer1 Input Capture Vector Address
+.equ	OC1Aaddr=$006	;Timer1 Output Compare A Interrupt Vector Address
+.equ	OC1Baddr=$007	;Timer1 Output Compare B Interrupt Vector Address
+.equ	OVF1addr=$008	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$009	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$00A	;SPI Interrupt Vector Address
+.equ	URXCaddr=$00B	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00C	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00D	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$00E	;ADC Conversion Complete Interrupt Vector Address
+.equ	ERDYaddr=$00F	;EEPROM Write Complete Interrupt Vector Address
+.equ	ACIaddr =$010	;Analog Comparator Interrupt Vector Address
\ No newline at end of file
diff --git a/include/8515def.inc b/include/8515def.inc
new file mode 100644
index 0000000..e4ddae7
--- /dev/null
+++ b/include/8515def.inc
@@ -0,0 +1,340 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"8515def.inc"
+;* Title				:Register/Bit Definitions for the AT90S8515
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.com
+;* Target MCU			:AT90S8515
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S8515
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$25
+.equ	ICR1L	=$24
+.equ	WDTCR	=$21
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	USR		=$0b
+.equ	UCR		=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+
+;***** Bit Definitions
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+;TIMSK
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ	TICIE1	=3
+.equ	TOIE0	=1
+
+;TIFR
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	ICF1	=3
+.equ	TOV0	=1
+
+;MCUCR
+.equ	SRE	=7
+.equ	SRW	=6
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7		=7
+.equ	PC6		=6
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;SPCR
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+;USR
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+
+;UCR
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;ACSR
+.equ	ACD		=7
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND  =$25F	;Last On-Chip SRAM Location
+.equ	XRAMEND =$FFFF
+.equ	E2END	=$1FF
+.equ	FLASHEND=$FFF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$004	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$005	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$006	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$007	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$008	;SPI Interrupt Vector Address
+.equ	URXCaddr=$009	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00a	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00b	;UART Transmit Complete Interrupt Vector Address
+.equ	ACIaddr =$00c	;Analog Comparator Interrupt Vector Address
diff --git a/include/8534def.inc b/include/8534def.inc
new file mode 100644
index 0000000..c3e857e
--- /dev/null
+++ b/include/8534def.inc
@@ -0,0 +1,161 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"8534def.inc"
+;* Title				:Register/Bit Definitions for the AT90C8534
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.com
+;* Target MCU			:AT90C8534
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;*
+;***** Specify Device
+.device AT90C8534
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ    MCUCR   =$35
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	GIPR	=$10
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+
+;***** Bit Definitions
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+;GIPR
+.equ	IPIN1	=3
+.equ	IPIN0	=2
+
+;TIMSK
+.equ    TOIE1   =2
+.equ    TOIE0   =0
+
+;TIFR
+.equ    TOV1    =2
+.equ    TOV0    =0
+
+;MCUCR
+.equ    SE      =6
+.equ    SM      =5
+.equ    ISC1    =2
+.equ    ISC0    =0
+
+;TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;ADMUX
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND	=$15f
+.equ	XRAMEND =$15F
+.equ	E2END	=$1FF
+.equ	FLASHEND=$FFF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	OVF1addr=$003	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$004	;Overflow0 Interrupt Vector Address
+.equ	ADCCaddr =$005	;ADC Interrupt Vector Address
+.equ	ERDYaddr =$006	;EEPROM Interrupt Vector Address
diff --git a/include/8535def.inc b/include/8535def.inc
new file mode 100644
index 0000000..07ad8a8
--- /dev/null
+++ b/include/8535def.inc
@@ -0,0 +1,391 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"8535def.inc"
+;* Title				:Register/Bit Definitions for the AT90S8535
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.com
+;* Target MCU			:AT90S8535
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device AT90S8535
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	USR		=$0b
+.equ	UCR		=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+
+
+;***** Bit Definitions
+;MCUSR
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+;TIMSK
+.equ	OCIE2	=7
+.equ	TOIE2	=6
+.equ	TICIE1	=5
+.equ	OCIE1A	=4
+.equ	OCIE1B	=3
+.equ	TOIE1	=2
+.equ	TOIE0	=0
+
+;TIFR
+.equ	OCF2	=7
+.equ	TOV2	=6
+.equ	ICF1	=5
+.equ	OCF1A	=4
+.equ	OCF1B	=3
+.equ	TOV1	=2
+.equ	TOV0	=0
+
+;MCUCR
+.equ	SE		=6
+.equ	SM1		=5
+.equ	SM0		=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	PWM2	=6
+.equ	COM21	=5
+.equ	COM20	=4
+.equ	CTC2	=3
+.equ	CS22	=2
+.equ	CS21	=1
+.equ	CS20	=0
+
+;ASSR
+.equ	AS2		=3
+.equ	TCN2UB	=2
+.equ	OCR2UB	=1
+.equ	TCR2UB	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ	EERIE	=3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7		=7
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7		=7
+.equ	PC6		=6
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;SPCR
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+;USR
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+
+;RXCIE
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;ACSR
+.equ	ACD		=7
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ	MUX2	=2
+.equ	MUX1	=1
+.equ	MUX0	=0
+
+;ADCSR
+.equ	ADEN	=7
+.equ	ADSC	=6
+.equ	ADFR	=5
+.equ	ADIF	=4
+.equ	ADIE	=3
+.equ	ADPS2	=2
+.equ	ADPS1	=1
+.equ	ADPS0	=0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND  =$25F	;Last On-Chip SRAM location
+.equ	XRAMEND =$25F
+.equ	E2END	=$1FF
+.equ	FLASHEND=$FFF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	OC2addr =$003	;Timer2 compare match Vector Address
+.equ	OVF2addr=$004	;Timer2 overflow Vector Address
+.equ	ICP1addr=$005	;Timer1 Input Capture Vector Address
+.equ	OC1Aaddr=$006	;Timer1 Output Compare A Interrupt Vector Address
+.equ	OC1Baddr=$007	;Timer1 Output Compare B Interrupt Vector Address
+.equ	OVF1addr=$008	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$009	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$00A	;SPI Interrupt Vector Address
+.equ	URXCaddr=$00B	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00C	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00D	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$00E	;ADC Conversion Complete Interrupt Vector Address
+.equ	ERDYaddr=$00F	;EEPROM Write Complete Interrupt Vector Address
+.equ	ACIaddr =$010	;Analog Comparator Interrupt Vector Address
diff --git a/include/AT86RF401def.inc b/include/AT86RF401def.inc
new file mode 100644
index 0000000..244bcc0
--- /dev/null
+++ b/include/AT86RF401def.inc
@@ -0,0 +1,200 @@
+;****************************************************************************************
+;* This can be included in the assembly file
+;* in order to use the names in the spec sheet.
+;* 
+;* I/O Register Definitions per AT86RF401 spec
+;****************************************************************************************
+
+;***** device directive, will make the assembler check for illegal instructions.
+.device AT86RF401
+
+;***** I/O Register Definitions
+.equ	SREG		=$3F    ; Status 
+.equ	SPH     	=$3E    ; Stack Pointer High 
+.equ	SPL     	=$3D    ; Stack Pointer Low 
+.equ	BL_CONFIG	=$35    ; Battery Low Configuration 
+.equ	B_DET   	=$34    ; Button Detect 
+.equ	PWR_CTL 	=$33    ; Power Control 
+.equ	IO_DATIN 	=$32    ; I/O Data In 
+.equ	IO_DATOUT 	=$31    ; I/O Data Out 
+.equ	IO_ENAB 	=$30    ; I/O Enable
+.equ	WDTCR 	    =$22    ; Watchdog Timer Control
+.equ	BTCR 		=$21    ; Bit Timer Control
+.equ	BTCNT 	    =$20    ; Bit Timer Count
+.equ	DEEAR	 	=$1E    ; Data EEPROM Address
+.equ	DEEDR	 	=$1D    ; Data EEPROM Data
+.equ	DEECR	 	=$1C    ; Data EEPROM Control
+.equ	LOCKDET2 	=$17    ; Lock Detector Configuration Register 2
+.equ	VCOTUNE 	=$16    ; VCO Tuning Register
+.equ	PWR_ATTEN 	=$14    ; Power Attenuation Control Register
+.equ	TX_CNTL	    =$12    ; Transmitter Control Register
+.equ	LOCKDET1 	=$10    ; Lock Detector Configuration Register 1
+.equ	SRAM_START 	=$0060	; Start of RAM
+.equ	SRAM_END 	=$00DF	; End of RAM
+
+;**** Bit Definitions
+; SREG
+.equ	I		=7
+.equ	T		=6
+.equ	H		=5
+.equ	S		=4
+.equ	V		=3
+.equ	N		=2
+.equ	Z		=1
+.equ	C		=0
+
+; BL_CONFIG
+.equ	BL		=7
+.equ	BLV		=6
+.equ	BL5		=5
+.equ	BL4		=4
+.equ	BL3		=3
+.equ	BL2		=2
+.equ	BL1		=1
+.equ	BL0		=0
+
+; B_DET
+.equ	BD5		=5
+.equ	BD4		=4
+.equ	BD3		=3
+.equ	BD2		=2
+.equ	BD1		=1
+.equ	BD0		=0
+
+; PWR_CTL
+.equ	ACS2	=7
+.equ	ACS1	=6
+.equ	ACS0	=5
+.equ	TM		=4
+.equ	BD		=3
+.equ	BLI		=2
+.equ	SLEEP	=1
+.equ	BBM		=0
+
+; IO_DATIN
+.equ	IOI5	=5
+.equ	IOI4	=4
+.equ	IOI3	=3
+.equ	IOI2	=2
+.equ	IOI1	=1
+.equ	IOI0	=0
+
+; IO_DATOUT
+.equ	IOO5	=5
+.equ	IOO4	=4
+.equ	IOO3	=3
+.equ	IOO2	=2
+.equ	IOO1	=1
+.equ	IOO0	=0
+
+; IO_ENAB
+.equ	BOHYST	=6
+.equ	IOE5	=5
+.equ	IOE4	=4
+.equ	IOE3	=3
+.equ	IOE2	=2
+.equ	IOE1	=1
+.equ	IOE0	=0
+
+; WDTCR
+.equ	WDTOE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+; BTCR
+.equ	C9		=7
+.equ	C8		=6
+.equ	M1		=5
+.equ	M0		=4
+.equ	IE		=3
+.equ	F2		=2
+.equ	DATA	=1
+.equ	F0		=0
+
+; BTCNT
+.equ	C7		=7
+.equ	C6		=6
+.equ	C5		=5
+.equ	C4		=4
+.equ	C3		=3
+.equ	C2		=2
+.equ	C1		=1
+.equ	C0		=0
+
+; DEEAR
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+; DEEDR
+.equ	ED7		=7
+.equ	ED6		=6
+.equ	ED5		=5
+.equ	ED4		=4
+.equ	ED3		=3
+.equ	ED2		=2
+.equ	ED1		=1
+.equ	ED0		=0
+
+; DEECR
+.equ	BSY		=3
+.equ	EEU		=2
+.equ	EEL		=1
+.equ	EER		=0
+
+; LOCKDET2
+.equ	EUD		=7
+.equ	LAT		=6
+.equ	ULC2	=5
+.equ	ULC1	=4
+.equ	ULC0	=3
+.equ	LC2		=2
+.equ	LC1		=1
+.equ	LC0		=0
+
+; VCOTUNE
+.equ	VCOVDET1	=7
+.equ	VCOVDET0	=6
+.equ	VCOTUNE4	=4
+.equ	VCOTUNE3	=3
+.equ	VCOTUNE2	=2
+.equ	VCOTUNE1	=1
+.equ	VCOTUNE0	=0
+
+; PWR_ATTEN
+.equ	PCC2	=5
+.equ	PCC1	=4
+.equ	PCC0	=3
+.equ	PCF2	=2
+.equ	PCF1	=1
+.equ	PCF0	=0
+
+; TX_CNTL
+.equ	FSK		=6
+.equ	TXE		=5
+.equ	TXK		=4
+.equ	LOC		=2
+
+; LOCKDET1
+.equ	UPOK	=4
+.equ	ENKO	=3
+.equ	BOD		=2
+.equ	CS1		=1
+.equ	CS0		=0
+
+;****************************************************************************************
+;* Define global registers
+;****************************************************************************************
+
+.def         XL      =R26   
+.def         XH      =R27   
+.def         YL      =R28   
+.def         YH      =R29   
+.def         ZL      =R30   
+.def         ZH      =R31   
diff --git a/include/m103def.inc b/include/m103def.inc
new file mode 100644
index 0000000..1f0a661
--- /dev/null
+++ b/include/m103def.inc
@@ -0,0 +1,429 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"m103def.inc"
+;* Title		:Register/Bit Definitions for the ATmega103
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	:avr@atmel.com
+;* Target MCU		:ATmega103
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega103
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH	=$3e
+.equ	SPL	=$3d
+.equ    XDIV	=$3c
+.equ    RAMPZ   =$3b
+.equ    EICR    =$3a
+.equ	EIMSK	=$39
+.equ	EIFR	=$38
+.equ	TIMSK	=$37
+.equ	TIFR	=$36
+.equ	MCUCR	=$35
+.equ    MCUSR   =$34
+
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	OCR0	=$31
+.equ    ASSR0   =$30
+
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+
+.equ    TCCR2   =$25
+.equ    TCNT2   =$24
+.equ    OCR2    =$23
+.equ	WDTCR	=$21
+
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	=$0c
+.equ	USR	=$0b
+.equ	UCR	=$0a
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    PORTE   =$03
+.equ    DDRE    =$02
+.equ    PINE    =$01
+.equ    PINF    =$00
+
+;***** Bit Definitions
+
+.equ 	RAMPZ0	=0
+
+.equ	SRE	=7
+.equ	SRW	=6
+.equ	SE	=5
+.equ	SM1	=4
+.equ	SM0	=3
+
+.equ	XDIVEN	=7
+.equ	XDIV6	=6
+.equ	XDIV5	=5
+.equ	XDIV4	=4
+.equ	XDIV3	=3
+.equ	XDIV2	=2
+.equ	XDIV1	=1
+.equ	XDIV0	=0
+
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT7	=7
+.equ	INT6	=6
+.equ	INT5	=5
+.equ	INT4	=4
+.equ	INT3	=3
+.equ	INT2	=2
+.equ	INT1	=1
+.equ	INT0	=0
+
+.equ	INTF7	=7
+.equ	INTF6	=6
+.equ	INTF5	=5
+.equ	INTF4	=4
+
+.equ	ISC71	=7
+.equ	ISC70	=6
+.equ	ISC61	=5
+.equ	ISC60	=4
+.equ	ISC51	=3
+.equ	ISC50	=2
+.equ	ISC41	=1
+.equ	ISC40	=0
+
+.equ	OCIE2	=7
+.equ	TOIE2	=6
+.equ	TICIE1	=5
+.equ	OCIE1A	=4
+.equ	OCIE1B	=3
+.equ	TOIE1	=2
+.equ	OCIE0	=1
+.equ	TOIE0	=0
+
+.equ	OCF2	=7
+.equ	TOV2	=6
+.equ	ICF1	=5
+.equ	OCF1A	=4
+.equ	OCF1B	=3
+.equ	TOV1	=2
+.equ	OCF0	=1
+.equ	TOV0	=0
+
+.equ    PWM0    =6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	CTC0	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ    PWM2    =6
+.equ	COM21	=5
+.equ	COM20	=4
+.equ	CTC2	=3
+.equ	CS22	=2
+.equ	CS21	=1
+.equ	CS20	=0
+
+.equ	AS0	=3
+.equ	TCN0UB	=2
+.equ	OCR0UB	=1
+.equ	TCR0UB	=0
+
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ    EERIE	=3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+.equ	PE7	=7
+.equ	PE6	=6
+.equ	PE5	=5
+.equ	PE4	=4
+.equ	PE3	=3
+.equ	PE2	=2
+.equ	PE1	=1
+.equ	PE0	=0
+
+.equ	DDE7	=7
+.equ	DDE6	=6
+.equ	DDE5	=5
+.equ	DDE4	=4
+.equ	DDE3	=3
+.equ	DDE2	=2
+.equ	DDE1	=1
+.equ	DDE0	=0
+
+.equ	PINE7	=7
+.equ	PINE6	=6
+.equ	PINE5	=5
+.equ	PINE4	=4
+.equ	PINE3	=3
+.equ	PINE2	=2
+.equ	PINE1	=1
+.equ	PINE0	=0
+
+.Equ	PINF7	=7
+.Equ	PINF6	=6
+.Equ	PINF5	=5
+.Equ	PINF4	=4
+.Equ	PINF3	=3
+.Equ	PINF2	=2
+.Equ	PINF1	=1
+.Equ	PINF0	=0
+
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+.equ	SPIF	=7
+.equ	WCOL	=6
+
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3
+
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+.equ	ACD	=7
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.equ	ADEN	=7
+.equ	ADSC	=6
+.equ	ADFR	=5
+.equ	ADIF	=4
+.equ	ADIE	=3
+.equ	ADPS2	=2
+.equ	ADPS1	=1
+.equ	ADPS0	=0
+
+.equ	MUX2	=2
+.equ	MUX1	=1
+.equ	MUX0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND 	=$0FFF	;Last On-Chip SRAM Location
+.equ	XRAMEND =$FFFF
+.equ	E2END	=$0FFF
+.equ	FLASHEND=$FFFF
+
+.equ	INT0addr=$002	;External Interrupt0 Vector Address
+.equ	INT1addr=$004	;External Interrupt1 Vector Address
+.equ	INT2addr=$006	;External Interrupt2 Vector Address
+.equ	INT3addr=$008	;External Interrupt3 Vector Address
+.equ	INT4addr=$00a	;External Interrupt4 Vector Address
+.equ	INT5addr=$00c	;External Interrupt5 Vector Address
+.equ	INT6addr=$00e	;External Interrupt6 Vector Address
+.equ	INT7addr=$010	;External Interrupt7 Vector Address
+.equ	OC2addr =$012	;Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$014	;Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$016	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$018	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$01a	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$01c	;Overflow1 Interrupt Vector Address
+.equ	OC0addr =$01e	;Output Compare0 Interrupt Vector Address
+.equ	OVF0addr=$020	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$022	;SPI Interrupt Vector Address
+.equ	URXCaddr=$024	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$026	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$028	;UART Transmit Complete Interrupt Vector Address
+.equ    ADCCaddr=$02a   ;ADC Conversion Complete Handle
+.equ    EEWRaddr=$02c   ;EEPROM Write Complete Handle
+.equ	ACIaddr =$02e	;Analog Comparator Interrupt Vector Address
+
diff --git a/include/m104def.inc b/include/m104def.inc
new file mode 100644
index 0000000..e1b75c3
--- /dev/null
+++ b/include/m104def.inc
@@ -0,0 +1,865 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		: AVR000
+;* File Name		: "m104def.inc"
+;* Title		: Register/Bit Definitions for the ATmega104
+;* Date                 : January 25th, 2000
+;* Version              : 1.0
+;* Support telephone	: +47 72 88 43 88 (ATMEL Norway)
+;* Support fax		: +47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	: support@atmel.no
+;* Target MCU		: ATmega104
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+;$Author: hackbard $
+;$Date: 2003-12-06 01:15:10 $
+;$Revision: 1.1 $
+;$Source: /chroot/cvs/my-code/atmel/include/m104def.inc,v $
+
+;**** Specify Device ****
+;.device ATmega104
+
+
+;*****************************************************************************
+; I/O Register Definitions
+;*****************************************************************************
+
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
+.equ	UCSR1C	= $9D
+.equ	UDR1	= $9C
+.equ	UCSR1A	= $9B
+.equ	UCSR1B	= $9A
+.equ	UBRR1L	= $99
+.equ	UBRR1H	= $98
+	
+.equ	UCSR0C	= $95
+	
+.equ	UBRR0H	= $90
+
+.equ	TCCR3C	= $8C
+.equ	TCCR3A	= $8B
+.equ	TCCR3B	= $8A
+.equ	TCNT3H	= $89
+.equ	TCNT3L	= $88
+.equ	OCR3AH	= $87
+.equ	OCR3AL	= $86
+.equ	OCR3BH	= $85
+.equ	OCR3BL	= $84
+.equ	OCR3CH	= $83
+.equ	OCR3CL	= $82
+.equ	ICR3H	= $81
+.equ	ICR3L	= $80
+
+.equ	ETIMSK	= $7D
+.equ	ETIFR	= $7C
+
+.equ	TCCR1C	= $7A
+.equ	OCR1CH	= $79
+.equ	OCR1CL	= $78
+
+.equ	TWCR	= $74
+.equ	TWDR	= $73
+.equ	TWAR	= $72
+.equ	TWSR	= $71
+.equ	TWBR	= $70
+	
+.equ	OSCCAL	= $6F
+
+.equ	XMCRA	= $6D
+.equ	XMCRB	= $6C
+
+.equ	EICRA	= $6A
+
+.equ	SPMCSR	= $68
+.equ	SPMCR	= $68		; old name for SPMCSR
+
+.equ	PORTG	= $65
+.equ	DDRG	= $64
+.equ	PING	= $63
+
+.equ	PORTF	= $62
+.equ	DDRF	= $61
+
+;**** I/O Register Definitions ($3F-$00) ****
+.equ	SREG	= $3F
+.equ	SPH	= $3E
+.equ	SPL	= $3D
+.equ	XDIV	= $3C
+.equ	RAMPZ	= $3B
+.equ	EICRB	= $3A
+.equ	EIMSK	= $39
+.equ	GIMSK	= $39		; old name for EIMSK
+.equ	GICR	= $39		; old name for EIMSK
+.equ	EIFR	= $38
+.equ	GIFR	= $38		; old name for EIFR
+.equ	TIMSK	= $37
+.equ	TIFR	= $36
+.equ	MCUCR	= $35
+.equ	MCUCSR	= $34
+.equ	TCCR0	= $33
+.equ	TCNT0	= $32
+.equ	OCR0	= $31
+.equ	ASSR	= $30
+.equ	TCCR1A	= $2F
+.equ	TCCR1B	= $2E
+.equ	TCNT1H	= $2D
+.equ	TCNT1L	= $2C
+.equ	OCR1AH	= $2B
+.equ	OCR1AL	= $2A
+.equ	OCR1BH	= $29
+.equ	OCR1BL	= $28
+.equ	ICR1H	= $27
+.equ	ICR1L	= $26
+.equ	TCCR2	= $25
+.equ	TCNT2	= $24
+.equ	OCR2	= $23
+.equ	OCDR	= $22		; New
+.equ	WDTCR	= $21
+.equ	SFIOR	= $20		; New
+.equ	EEARH	= $1F
+.equ	EEARL	= $1E
+.equ	EEDR	= $1D
+.equ	EECR	= $1C
+.equ	PORTA	= $1B
+.equ	DDRA	= $1A
+.equ	PINA	= $19
+.equ	PORTB	= $18
+.equ	DDRB	= $17
+.equ	PINB	= $16
+.equ	PORTC	= $15
+.equ	DDRC	= $14		; New
+.equ	PINC	= $13		; New
+.equ	PORTD	= $12
+.equ	DDRD	= $11
+.equ	PIND	= $10
+.equ	SPDR	= $0F
+.equ	SPSR	= $0E
+.equ	SPCR	= $0D
+.equ	UDR0	= $0C
+.equ	UCSR0A	= $0B
+.equ	UCSR0B	= $0A
+.equ	UBRR0L	= $09
+.equ	ACSR	= $08
+.equ	ADMUX	= $07
+.equ	ADCSR	= $06
+.equ	ADCH	= $05
+.equ	ADCL	= $04
+.equ	PORTE	= $03
+.equ	DDRE	= $02
+.equ	PINE	= $01
+.equ	PINF	= $00
+
+
+;*****************************************************************************
+; Bit Definitions
+;*****************************************************************************
+
+;**** MCU Control ****
+.equ	SRE	= 7		; MCUCR
+.equ	SRW10	= 6
+.equ	SE	= 5
+.equ	SM1	= 4
+.equ	SM0	= 3
+.equ	SM2	= 2
+.equ	IVSEL	= 1
+.equ	IVCE	= 0
+
+.equ	JTD	= 7		; MCUCSR
+.equ	JTRF	= 4	
+.equ	WDRF	= 3
+.equ	BORF	= 2
+.equ	EXTRF	= 1
+.equ	PORF	= 0
+
+.equ	SRL2	=6		; XMCRA
+.equ	SRL1	=5
+.equ	SRL0	=4
+.equ	SRW01	=3
+.equ	SRW00	=2
+.equ	SRW11	=1
+
+.equ	XMBK	= 7		; XMCRB
+.equ	XMM2	= 2
+.equ	XMM1	= 1
+.equ	XMM0	= 0
+
+.equ	SPMIE	=7		; SPMCSR
+.equ	ASB	=6		; backwards compatiblity
+.equ	ASRE	=4		; backwards compatiblity
+.equ	RWWSB	=6
+.equ	RWWSRE	=4	
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+.equ	IDRD	= 7		; OCDR
+.equ	OCDR6	= 6
+.equ	OCDR5	= 5
+.equ	OCDR4	= 4	
+.equ	OCDR3	= 3
+.equ	OCDR2	= 2
+.equ	OCDR1	= 1
+.equ	OCDR0	= 0
+
+.equ	XDIVEN	= 7		; XDIV
+.equ	XDIV6	= 6
+.equ	XDIV5	= 5
+.equ	XDIV4	= 4
+.equ	XDIV3	= 3
+.equ	XDIV2	= 2
+.equ	XDIV1	= 1
+.equ	XDIV0	= 0
+
+.equ	TSM	= 7		; SFIOR
+.equ	ADHSM	= 4
+.equ	ACME	= 3
+.equ	PUD	= 2
+.equ	PSR0	= 1
+.equ	PSR1	= 0
+.equ	PSR2	= 0
+.equ	PSR3	= 0
+.equ	PSR321	= 0	
+
+;**** Analog to Digital Converter ****
+.equ	ADEN	= 7		; ADCSR
+.equ	ADSC	= 6
+.equ	ADFR	= 5
+.equ	ADIF	= 4
+.equ	ADIE	= 3
+.equ	ADPS2	= 2
+.equ	ADPS1	= 1
+.equ	ADPS0	= 0
+
+.equ    REFS1   =7		; ADMUX
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;**** Analog Comparator ****
+.equ	ACD	= 7		; ACSR
+.equ	ACBG	= 6
+.equ	ACO	= 5
+.equ	ACI	= 4
+.equ	ACIE	= 3
+.equ	ACIC	= 2
+.equ	ACIS1	= 1
+.equ	ACIS0	= 0
+	
+
+;**** External Interrupts ****
+.equ	INT7	= 7		; EIMSK
+.equ	INT6	= 6
+.equ	INT5	= 5
+.equ	INT4	= 4
+.equ	INT3	= 3
+.equ	INT2	= 2
+.equ	INT1	= 1
+.equ	INT0	= 0
+
+.equ	INTF7	= 7		; EIFR
+.equ	INTF6	= 6
+.equ	INTF5	= 5
+.equ	INTF4	= 4
+.equ	INTF3	= 3
+.equ	INTF2	= 2
+.equ	INTF1	= 1
+.equ	INTF0	= 0
+
+.equ	ISC71	= 7		; EICRB
+.equ	ISC70	= 6
+.equ	ISC61	= 5
+.equ	ISC60	= 4
+.equ	ISC51	= 3
+.equ	ISC50	= 2
+.equ	ISC41	= 1
+.equ	ISC40	= 0
+
+.equ	ISC31	= 7		; EICRA
+.equ	ISC30	= 6
+.equ	ISC21	= 5
+.equ	ISC20	= 4
+.equ	ISC11	= 3
+.equ	ISC10	= 2
+.equ	ISC01	= 1
+.equ	ISC00	= 0
+
+;**** Timer Interrupts ****
+.equ	OCIE2	= 7		; TIMSK
+.equ	TOIE2	= 6
+.equ	TICIE1	= 5
+.equ	OCIE1A	= 4
+.equ	OCIE1B	= 3
+.equ	TOIE1	= 2
+.equ	OCIE0	= 1
+.equ	TOIE0	= 0
+
+.equ	TICIE3	= 5		; ETIMSK
+.equ	OCIE3A	= 4
+.equ	OCIE3B	= 3
+.equ	TOIE3	= 2
+.equ	OCIE3C	= 1
+.equ	OCIE1C	= 0
+
+.equ	OCF2	= 7		; TIFR
+.equ	TOV2	= 6
+.equ	ICF1	= 5
+.equ	OCF1A	= 4
+.equ	OCF1B	= 3
+.equ	TOV1	= 2
+.equ	OCF0	= 1
+.equ	TOV0	= 0
+
+.equ	ICF3	= 5		; ETIFR
+.equ	OCF3A	= 4
+.equ	OCF3B	= 3
+.equ	TOV3	= 2
+.equ	OCF3C	= 1
+.equ	OCF1C	= 0
+
+;**** Asynchronous Timer ****
+.equ	AS0	= 3		; ASSR
+.equ	TCN0UB	= 2
+.equ	OCR0UB	= 1
+.equ	TCR0UB	= 0
+
+;**** Timer 0 ****
+.equ    FOC0    = 7		; TCCR0
+.equ    PWM0    = 6
+.equ	COM01	= 5
+.equ	COM00	= 4
+.equ	CTC0	= 3
+.equ	CS02	= 2
+.equ	CS01	= 1
+.equ	CS00	= 0
+
+;**** Timer 1 ****
+.equ	COM1A1	= 7		; TCCR1A
+.equ	COM1A0	= 6
+.equ	COM1B1	= 5
+.equ	COM1B0	= 4
+.equ	COM1C1	= 3
+.equ	COM1C0	= 2
+.equ	PWM11	= 1		; OBSOLETE! Use WGM11
+.equ	PWM10	= 0		; OBSOLETE! Use WGM10
+.equ	WGM11	= 1
+.equ	WGM10	= 0
+
+.equ	ICNC1	= 7		; TCCR1B
+.equ	ICES1	= 6
+.equ	CTC11	= 4		; OBSOLETE! Use WGM13
+.equ	CTC10	= 3		; OBSOLETE! Use WGM12
+.equ	WGM13	= 4
+.equ	WGM12	= 3
+.equ	CS12	= 2
+.equ	CS11	= 1
+.equ	CS10	= 0
+
+.equ	FOC1A	= 7		; TCCR1C
+.equ	FOC1B	= 6
+.equ	FOC1C	= 5
+
+;**** Timer 2 ****
+.equ	FOC2	= 7		; TCCR2
+.equ	PWM2	= 6
+.equ	COM21	= 5
+.equ	COM20	= 4
+.equ	CTC2	= 3
+.equ	CS22	= 2
+.equ	CS21	= 1
+.equ	CS20	= 0
+
+;**** Timer 3 ****
+.equ	COM3A1	= 7		; TCCR3A
+.equ	COM3A0	= 6
+.equ	COM3B1	= 5
+.equ	COM3B0	= 4
+.equ	COM3C1	= 3
+.equ	COM3C0	= 2
+.equ	PWM31	= 1		; OBSOLETE! Use WGM31
+.equ	PWM30	= 0		; OBSOLETE! Use WGM30
+.equ	WGM31	= 1
+.equ	WGM30	= 0
+
+.equ	ICNC3	= 7		; TCCR3B
+.equ	ICES3	= 6
+.equ	CTC31	= 4		; OBSOLETE! Use WGM33
+.equ	CTC30	= 3		; OBSOLETE! Use WGM32
+.equ	WGM33	= 4
+.equ	WGM32	= 3
+.equ	CS32	= 2
+.equ	CS31	= 1
+.equ	CS30	= 0
+
+.equ	FOC3A	= 7		; TCCR3C
+.equ	FOC3B	= 6
+.equ	FOC3C	= 5
+
+;**** Watchdog Timer ****
+.equ	WDCE	= 4		; WDTCR
+.equ	WDTOE	= 4		; For Mega103 compability
+.equ	WDE	= 3
+.equ	WDP2	= 2
+.equ	WDP1	= 1
+.equ	WDP0	= 0
+
+;**** EEPROM  Control Register ****
+.equ	EERIE	= 3		; EECR
+.equ	EEMWE	= 2
+.equ	EEWE	= 1
+.equ	EERE	= 0
+
+;**** USART 0 and USART 1 ****
+.equ	RXC	= 7		; (UCSRA0/1)
+.equ	TXC	= 6
+.equ	UDRE	= 5
+.equ	FE	= 4
+.equ	DOR	= 3
+.equ	PE	= 2		; OBSOLETED!
+.equ	U2X	= 1
+.equ	MPCM	= 0
+
+.equ	RXC0	= 7		; (UCSR0A)
+.equ	TXC0	= 6
+.equ	UDRE0	= 5
+.equ	FE0	= 4
+.equ	DOR0	= 3
+.equ	UPE0	= 2
+.equ	U2X0	= 1
+.equ	MPCM0	= 0
+
+.equ	RXC1	= 7		; (UCSR1A)
+.equ	TXC1	= 6
+.equ	UDRE1	= 5
+.equ	FE1	= 4
+.equ	DOR1	= 3
+.equ	UPE1	= 2
+.equ	U2X1	= 1
+.equ	MPCM1	= 0
+
+.equ	RXCIE	= 7		; (UCSRB0/1)
+.equ	TXCIE	= 6
+.equ	UDRIE	= 5
+.equ	RXEN	= 4
+.equ	TXEN	= 3
+.equ	UCSZ2	= 2
+.equ	RXB8	= 1
+.equ	TXB8	= 0
+
+.equ	RXCIE0	= 7		; (UCSR0B)
+.equ	TXCIE0	= 6
+.equ	UDRIE0	= 5
+.equ	RXEN0	= 4
+.equ	TXEN0	= 3
+.equ	UCSZ02	= 2
+.equ	RXB80	= 1
+.equ	TXB80	= 0
+
+.equ	RXCIE1	= 7		; (UCSR1B)
+.equ	TXCIE1	= 6
+.equ	UDRIE1	= 5
+.equ	RXEN1	= 4
+.equ	TXEN1	= 3
+.equ	UCSZ12	= 2
+.equ	RXB81	= 1
+.equ	TXB81	= 0
+
+.equ	UMSEL	= 6		; (UCSRC0/1)
+.equ	UPM1	= 5
+.equ	UPM0	= 4
+.equ	USBS	= 3
+.equ	UCSZ1	= 2
+.equ	UCSZ0	= 1
+.equ	UCPOL	= 0
+
+.equ	UMSEL0	= 6		; (UCSR0C)
+.equ	UPM01	= 5
+.equ	UPM00	= 4
+.equ	USBS0	= 3
+.equ	UCSZ01	= 2
+.equ	UCSZ00	= 1
+.equ	UCPOL0	= 0
+
+.equ	UMSEL1	= 6		; (UCSR1C)
+.equ	UPM11	= 5
+.equ	UPM10	= 4
+.equ	USBS1	= 3
+.equ	UCSZ11	= 2
+.equ	UCSZ10	= 1
+.equ	UCPOL1	= 0
+
+	
+;**** SPI ****
+.equ	SPIE	= 7		; SPCR
+.equ	SPE	= 6
+.equ	DORD	= 5
+.equ	MSTR	= 4
+.equ	CPOL	= 3
+.equ	CPHA	= 2
+.equ	SPR1	= 1
+.equ	SPR0	= 0
+
+.equ	SPIF	= 7		; SPSR
+.equ	WCOL	= 6
+.equ	SPI2X	= 0
+
+;**** TWI ****
+	
+.equ	TWINT	= 7
+.equ	TWEA	= 6
+.equ	TWSTA	= 5
+.equ	TWSTO	= 4
+.equ	TWWC	= 3
+.equ    TWEN    = 2
+.equ	TWIE	= 0
+.equ	TWS7	= 7		; TWSR
+.equ	TWS6	= 6
+.equ	TWS5	= 5
+.equ	TWS4	= 4
+.equ	TWS3	= 3
+.equ	TWGCE	= 0		; TWAR
+
+		
+;**** PORT A ****
+.equ	PA7	= 7		; PORTA
+.equ	PA6	= 6
+.equ	PA5	= 5
+.equ	PA4	= 4
+.equ	PA3	= 3
+.equ	PA2	= 2
+.equ	PA1	= 1
+.equ	PA0	= 0
+.equ	PORTA7	= 7
+.equ	PORTA6	= 6
+.equ	PORTA5	= 5
+.equ	PORTA4	= 4
+.equ	PORTA3	= 3
+.equ	PORTA2	= 2
+.equ	PORTA1	= 1
+.equ	PORTA0	= 0
+
+.equ	DDA7	= 7		; DDRA
+.equ	DDA6	= 6
+.equ	DDA5	= 5
+.equ	DDA4	= 4
+.equ	DDA3	= 3
+.equ	DDA2	= 2
+.equ	DDA1	= 1
+.equ	DDA0	= 0
+
+.equ	PINA7	= 7		; PINA
+.equ	PINA6	= 6
+.equ	PINA5	= 5
+.equ	PINA4	= 4
+.equ	PINA3	= 3
+.equ	PINA2	= 2
+.equ	PINA1	= 1
+.equ	PINA0	= 0
+
+;**** PORT B ****
+.equ	PB7	= 7		; PORTB
+.equ	PB6	= 6
+.equ	PB5	= 5
+.equ	PB4	= 4
+.equ	PB3	= 3
+.equ	PB2	= 2
+.equ	PB1	= 1
+.equ	PB0	= 0
+.equ	PORTB7	= 7
+.equ	PORTB6	= 6
+.equ	PORTB5	= 5
+.equ	PORTB4	= 4
+.equ	PORTB3	= 3
+.equ	PORTB2	= 2
+.equ	PORTB1	= 1
+.equ	PORTB0	= 0
+
+.equ	DDB7	= 7		; DDRB
+.equ	DDB6	= 6
+.equ	DDB5	= 5
+.equ	DDB4	= 4
+.equ	DDB3	= 3
+.equ	DDB2	= 2
+.equ	DDB1	= 1
+.equ	DDB0	= 0
+
+.equ	PINB7	= 7		; PINB
+.equ	PINB6	= 6
+.equ	PINB5	= 5
+.equ	PINB4	= 4
+.equ	PINB3	= 3
+.equ	PINB2	= 2
+.equ	PINB1	= 1
+.equ	PINB0	= 0
+
+;**** PORT C ****
+.equ	PC7	= 7		; PORTC
+.equ	PC6	= 6
+.equ	PC5	= 5
+.equ	PC4	= 4
+.equ	PC3	= 3
+.equ	PC2	= 2
+.equ	PC1	= 1
+.equ	PC0	= 0
+.equ	PORTC7	= 7
+.equ	PORTC6	= 6
+.equ	PORTC5	= 5
+.equ	PORTC4	= 4
+.equ	PORTC3	= 3
+.equ	PORTC2	= 2
+.equ	PORTC1	= 1
+.equ	PORTC0	= 0
+
+.equ	DDC7	= 7		; DDRC
+.equ	DDC6	= 6
+.equ	DDC5	= 5
+.equ	DDC4	= 4
+.equ	DDC3	= 3
+.equ	DDC2	= 2
+.equ	DDC1	= 1
+.equ	DDC0	= 0
+
+.equ	PINC7	= 7		; PINC
+.equ	PINC6	= 6
+.equ	PINC5	= 5
+.equ	PINC4	= 4
+.equ	PINC3	= 3
+.equ	PINC2	= 2
+.equ	PINC1	= 1
+.equ	PINC0	= 0
+
+;**** PORT D ****
+.equ	PD7	= 7		; PORTD
+.equ	PD6	= 6
+.equ	PD5	= 5
+.equ	PD4	= 4
+.equ	PD3	= 3
+.equ	PD2	= 2
+.equ	PD1	= 1
+.equ	PD0	= 0
+.equ	PORTD7	= 7
+.equ	PORTD6	= 6
+.equ	PORTD5	= 5
+.equ	PORTD4	= 4
+.equ	PORTD3	= 3
+.equ	PORTD2	= 2
+.equ	PORTD1	= 1
+.equ	PORTD0	= 0
+
+.equ	DDD7	= 7		; DDRD
+.equ	DDD6	= 6
+.equ	DDD5	= 5
+.equ	DDD4	= 4
+.equ	DDD3	= 3
+.equ	DDD2	= 2
+.equ	DDD1	= 1
+.equ	DDD0	= 0
+
+.equ	PIND7	= 7		; PIND
+.equ	PIND6	= 6
+.equ	PIND5	= 5
+.equ	PIND4	= 4
+.equ	PIND3	= 3
+.equ	PIND2	= 2
+.equ	PIND1	= 1
+.equ	PIND0	= 0
+
+;**** PORT E ****
+.equ	PE7	= 7		; PORTE
+.equ	PE6	= 6
+.equ	PE5	= 5
+.equ	PE4	= 4
+.equ	PE3	= 3
+.equ	PE2	= 2
+.equ	PE1	= 1
+.equ	PE0	= 0
+.equ	PORTE7	= 7		; PORTE
+.equ	PORTE6	= 6
+.equ	PORTE5	= 5
+.equ	PORTE4	= 4
+.equ	PORTE3	= 3
+.equ	PORTE2	= 2
+.equ	PORTE1	= 1
+.equ	PORTE0	= 0
+
+.equ	DDE7	= 7		; DDRE
+.equ	DDE6	= 6
+.equ	DDE5	= 5
+.equ	DDE4	= 4
+.equ	DDE3	= 3
+.equ	DDE2	= 2
+.equ	DDE1	= 1
+.equ	DDE0	= 0
+
+.equ	PINE7	= 7		; PINE
+.equ	PINE6	= 6
+.equ	PINE5	= 5
+.equ	PINE4	= 4
+.equ	PINE3	= 3
+.equ	PINE2	= 2
+.equ	PINE1	= 1
+.equ	PINE0	= 0
+
+;**** PORT F ****
+.equ	PF7	= 7		; PORTF
+.equ	PF6	= 6
+.equ	PF5	= 5
+.equ	PF4	= 4
+.equ	PF3	= 3
+.equ	PF2	= 2
+.equ	PF1	= 1
+.equ	PF0	= 0
+.equ	PORTF7	= 7
+.equ	PORTF6	= 6
+.equ	PORTF5	= 5
+.equ	PORTF4	= 4
+.equ	PORTF3	= 3
+.equ	PORTF2	= 2
+.equ	PORTF1	= 1
+.equ	PORTF0	= 0
+
+.equ	DDF7	= 7		; DDRF
+.equ	DDF6	= 6
+.equ	DDF5	= 5
+.equ	DDF4	= 4
+.equ	DDF3	= 3
+.equ	DDF2	= 2
+.equ	DDF1	= 1
+.equ	DDF0	= 0
+
+.equ	PINF7	= 7		; PINF
+.equ	PINF6	= 6
+.equ	PINF5	= 5
+.equ	PINF4	= 4
+.equ	PINF3	= 3
+.equ	PINF2	= 2
+.equ	PINF1	= 1
+.equ	PINF0	= 0
+
+;**** PORT G ****
+.equ	PG4	= 4		; PORTG
+.equ	PG3	= 3
+.equ	PG2	= 2
+.equ	PG1	= 1
+.equ	PG0	= 0
+
+.equ	DDG4	= 4		; DDRG
+.equ	DDG3	= 3
+.equ	DDG2	= 2
+.equ	DDG1	= 1
+.equ	DDG0	= 0
+
+.equ	PING4	= 4		; PING
+.equ	PING3	= 3
+.equ	PING2	= 2
+.equ	PING1	= 1
+.equ	PING0	= 0
+
+
+;*****************************************************************************
+; CPU Register Declarations
+;*****************************************************************************
+
+.def	XL	= r26		; X pointer low
+.def	XH	= r27		; X pointer high
+.def	YL	= r28		; Y pointer low
+.def	YH	= r29		; Y pointer high
+.def	ZL	= r30		; Z pointer low
+.def	ZH	= r31		; Z pointer high
+
+
+;*****************************************************************************
+; Data Memory Declarations
+;*****************************************************************************
+
+.equ 	RAMEND	= $10ff		; Highest internal data memory (SRAM) address.
+.equ	EEPROMEND = $0fff       ; Highest EEPROM address.
+	
+;*****************************************************************************
+; Program Memory Declarations
+;*****************************************************************************
+
+.equ    FLASHEND = $FFFF	;  Highest program memory (flash) address
+	                        ; (When addressed as 16 bit words)
+		
+;**** Boot Vectors ****
+			 ;  byte groups
+			 ;  /--\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	= 0b1111111000000000	; ($FE00) Smallest boot block is 512W
+.equ 	SECONDBOOTSTART	= 0b1111110000000000	; ($FC00) 2'nd boot block size is 1KW
+.equ 	THIRDBOOTSTART	= 0b1111100000000000	; ($F800) Third boot block size is 2KW
+.equ 	LARGEBOOTSTART	= 0b1111000000000000	; ($F000) Largest boot block is 4KW
+
+
+;**** Page Size ****
+.equ	PAGESIZE	= 128	; Number of WORDS in a page
+
+
+;**** Interrupt Vectors ****
+.equ	INT0addr  = $002	; External Interrupt0 Vector Address
+.equ	INT1addr  = $004	; External Interrupt1 Vector Address
+.equ	INT2addr  = $006	; External Interrupt2 Vector Address
+.equ	INT3addr  = $008	; External Interrupt3 Vector Address
+.equ	INT4addr  = $00a	; External Interrupt4 Vector Address
+.equ	INT5addr  = $00c	; External Interrupt5 Vector Address
+.equ	INT6addr  = $00e	; External Interrupt6 Vector Address
+.equ	INT7addr  = $010	; External Interrupt7 Vector Address
+.equ	OC2addr   = $012	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr  = $014	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr  = $016	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr  = $018	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr  = $01a	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr  = $01c	; Overflow1 Interrupt Vector Address
+.equ	OC0addr   = $01e	; Output Compare0 Interrupt Vector Address
+.equ	OVF0addr  = $020	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr   = $022	; SPI Interrupt Vector Address
+.equ	URXC0addr = $024	; USART0 Receive Complete Interrupt Vector Address
+.equ	UDRE0addr = $026	; USART0 Data Register Empty Interrupt Vector Address
+.equ	UTXC0addr = $028	; USART0 Transmit Complete Interrupt Vector Address
+.equ    ADCCaddr  = $02a	; ADC Conversion Complete Handle
+.equ	ERDYaddr  = $02c	; EEPROM Write Complete Handle
+.equ	ACIaddr   = $02e	; Analog Comparator Interrupt Vector Address
+
+.equ	OC1Caddr  = $030	; Output Compare1C Interrupt Vector Address
+.equ	ICP3addr  = $032	; Input Capture3 Interrupt Vector Address
+.equ	OC3Aaddr  = $034	; Output Compare3A Interrupt Vector Address
+.equ	OC3Baddr  = $036	; Output Compare3B Interrupt Vector Address
+.equ	OC3Caddr  = $038	; Output Compare3C Interrupt Vector Address
+.equ	OVF3addr  = $03A	; Overflow3 Interrupt Vector Address
+.equ	URXC1addr = $03C	; USART1 Receive Complete Interrupt Vector Address
+.equ	UDRE1addr = $03E	; USART1 Data Register Empty Interrupt Vector Address
+.equ	UTXC1addr = $040	; USART1 Transmit Complete Interrupt Vector Address
+.equ    TWIaddr   = $042	; TWI Interrupt Vector Address
+.equ	SPMRaddr  = $044	; Store Program Memory Ready Interrupt Vector Address
+
+
+;**** End of File ****
diff --git a/include/m128def.inc b/include/m128def.inc
new file mode 100644
index 0000000..9032305
--- /dev/null
+++ b/include/m128def.inc
@@ -0,0 +1,858 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				: AVR000
+;* File Name			: "m128def.inc"
+;* Title				: Register/Bit Definitions for the ATmega128
+;* Date                 : 07.09.2001
+;* Version              : 1.0
+;* Support telephone	: +47 72 88 43 88 (ATMEL Norway)
+;* Support fax			: +47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		: avr@atmel.no
+;* Target MCU			: ATmega128
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;**** Specify Device ****
+.device ATmega128
+
+;*****************************************************************************
+; I/O Register Definitions
+;*****************************************************************************
+
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
+.equ	UCSR1C	= $9D
+.equ	UDR1	= $9C
+.equ	UCSR1A	= $9B
+.equ	UCSR1B	= $9A
+.equ	UBRR1L	= $99
+.equ	UBRR1H	= $98
+.equ	UCSR0C	= $95
+.equ	UBRR0H	= $90
+.equ	TCCR3C	= $8C
+.equ	TCCR3A	= $8B
+.equ	TCCR3B	= $8A
+.equ	TCNT3H	= $89
+.equ	TCNT3L	= $88
+.equ	OCR3AH	= $87
+.equ	OCR3AL	= $86
+.equ	OCR3BH	= $85
+.equ	OCR3BL	= $84
+.equ	OCR3CH	= $83
+.equ	OCR3CL	= $82
+.equ	ICR3H	= $81
+.equ	ICR3L	= $80
+.equ	ETIMSK	= $7D
+.equ	ETIFR	= $7C
+.equ	TCCR1C	= $7A
+.equ	OCR1CH	= $79
+.equ	OCR1CL	= $78
+.equ	TWCR	= $74
+.equ	TWDR	= $73
+.equ	TWAR	= $72
+.equ	TWSR	= $71
+.equ	TWBR	= $70
+.equ	OSCCAL	= $6F
+.equ	XMCRA	= $6D
+.equ	XMCRB	= $6C
+.equ	EICRA	= $6A
+.equ	SPMCSR	= $68
+.equ	SPMCR	= $68		; old name for SPMCSR
+.equ	PORTG	= $65
+.equ	DDRG	= $64
+.equ	PING	= $63
+.equ	PORTF	= $62
+.equ	DDRF	= $61
+
+;**** I/O Register Definitions ($3F-$00) ****
+.equ	SREG	= $3F
+.equ	SPH		= $3E
+.equ	SPL		= $3D
+.equ	XDIV	= $3C
+.equ	RAMPZ	= $3B
+.equ	EICRB	= $3A
+.equ	EIMSK	= $39
+.equ	GIMSK	= $39		; old name for EIMSK
+.equ	GICR	= $39		; old name for EIMSK
+.equ	EIFR	= $38
+.equ	GIFR	= $38		; old name for EIFR
+.equ	TIMSK	= $37
+.equ	TIFR	= $36
+.equ	MCUCR	= $35
+.equ	MCUCSR	= $34
+.equ	TCCR0	= $33
+.equ	TCNT0	= $32
+.equ	OCR0	= $31
+.equ	ASSR	= $30
+.equ	TCCR1A	= $2F
+.equ	TCCR1B	= $2E
+.equ	TCNT1H	= $2D
+.equ	TCNT1L	= $2C
+.equ	OCR1AH	= $2B
+.equ	OCR1AL	= $2A
+.equ	OCR1BH	= $29
+.equ	OCR1BL	= $28
+.equ	ICR1H	= $27
+.equ	ICR1L	= $26
+.equ	TCCR2	= $25
+.equ	TCNT2	= $24
+.equ	OCR2	= $23
+.equ	OCDR	= $22		; New
+.equ	WDTCR	= $21
+.equ	SFIOR	= $20		; New
+.equ	EEARH	= $1F
+.equ	EEARL	= $1E
+.equ	EEDR	= $1D
+.equ	EECR	= $1C
+.equ	PORTA	= $1B
+.equ	DDRA	= $1A
+.equ	PINA	= $19
+.equ	PORTB	= $18
+.equ	DDRB	= $17
+.equ	PINB	= $16
+.equ	PORTC	= $15
+.equ	DDRC	= $14		; New
+.equ	PINC	= $13		; New
+.equ	PORTD	= $12
+.equ	DDRD	= $11
+.equ	PIND	= $10
+.equ	SPDR	= $0F
+.equ	SPSR	= $0E
+.equ	SPCR	= $0D
+.equ	UDR0	= $0C
+.equ	UCSR0A	= $0B
+.equ	UCSR0B	= $0A
+.equ	UBRR0L	= $09
+.equ	ACSR	= $08
+.equ	ADMUX	= $07
+.equ	ADCSR	= $06
+.equ	ADCH	= $05
+.equ	ADCL	= $04
+.equ	PORTE	= $03
+.equ	DDRE	= $02
+.equ	PINE	= $01
+.equ	PINF	= $00
+
+
+;*****************************************************************************
+; Bit Definitions
+;*****************************************************************************
+
+;**** MCU Control ****
+.equ	SRE		= 7		; MCUCR
+.equ	SRW10	= 6
+.equ	SE		= 5
+.equ	SM1		= 4
+.equ	SM0		= 3
+.equ	SM2		= 2
+.equ	IVSEL	= 1
+.equ	IVCE	= 0
+
+.equ	JTD		= 7		; MCUCSR
+.equ	JTRF	= 4	
+.equ	WDRF	= 3
+.equ	BORF	= 2
+.equ	EXTRF	= 1
+.equ	PORF	= 0
+
+.equ	SRL2	=6		; XMCRA
+.equ	SRL1	=5
+.equ	SRL0	=4
+.equ	SRW01	=3
+.equ	SRW00	=2
+.equ	SRW11	=1
+
+.equ	XMBK	= 7		; XMCRB
+.equ	XMM2	= 2
+.equ	XMM1	= 1
+.equ	XMM0	= 0
+
+.equ	SPMIE	=7		; SPMCSR
+.equ	ASB		=6		; backwards compatiblity
+.equ	ASRE	=4		; backwards compatiblity
+.equ	RWWSB	=6
+.equ	RWWSRE	=4	
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+.equ	IDRD	= 7		; OCDR
+.equ	OCDR6	= 6
+.equ	OCDR5	= 5
+.equ	OCDR4	= 4	
+.equ	OCDR3	= 3
+.equ	OCDR2	= 2
+.equ	OCDR1	= 1
+.equ	OCDR0	= 0
+
+.equ	XDIVEN	= 7		; XDIV
+.equ	XDIV6	= 6
+.equ	XDIV5	= 5
+.equ	XDIV4	= 4
+.equ	XDIV3	= 3
+.equ	XDIV2	= 2
+.equ	XDIV1	= 1
+.equ	XDIV0	= 0
+
+.equ	TSM		= 7		; SFIOR
+.equ	ADHSM	= 4
+.equ	ACME	= 3
+.equ	PUD		= 2
+.equ	PSR0	= 1
+.equ	PSR1	= 0
+.equ	PSR2	= 0
+.equ	PSR3	= 0
+.equ	PSR321	= 0	
+
+;**** Analog to Digital Converter ****
+.equ	ADEN	= 7		; ADCSR
+.equ	ADSC	= 6
+.equ	ADFR	= 5
+.equ	ADIF	= 4
+.equ	ADIE	= 3
+.equ	ADPS2	= 2
+.equ	ADPS1	= 1
+.equ	ADPS0	= 0
+
+.equ    REFS1   =7		; ADMUX
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;**** Analog Comparator ****
+.equ	ACD		= 7		; ACSR
+.equ	ACBG	= 6
+.equ	ACO		= 5
+.equ	ACI		= 4
+.equ	ACIE	= 3
+.equ	ACIC	= 2
+.equ	ACIS1	= 1
+.equ	ACIS0	= 0
+	
+
+;**** External Interrupts ****
+.equ	INT7	= 7		; EIMSK
+.equ	INT6	= 6
+.equ	INT5	= 5
+.equ	INT4	= 4
+.equ	INT3	= 3
+.equ	INT2	= 2
+.equ	INT1	= 1
+.equ	INT0	= 0
+
+.equ	INTF7	= 7		; EIFR
+.equ	INTF6	= 6
+.equ	INTF5	= 5
+.equ	INTF4	= 4
+.equ	INTF3	= 3
+.equ	INTF2	= 2
+.equ	INTF1	= 1
+.equ	INTF0	= 0
+
+.equ	ISC71	= 7		; EICRB
+.equ	ISC70	= 6
+.equ	ISC61	= 5
+.equ	ISC60	= 4
+.equ	ISC51	= 3
+.equ	ISC50	= 2
+.equ	ISC41	= 1
+.equ	ISC40	= 0
+
+.equ	ISC31	= 7		; EICRA
+.equ	ISC30	= 6
+.equ	ISC21	= 5
+.equ	ISC20	= 4
+.equ	ISC11	= 3
+.equ	ISC10	= 2
+.equ	ISC01	= 1
+.equ	ISC00	= 0
+
+;**** Timer Interrupts ****
+.equ	OCIE2	= 7		; TIMSK
+.equ	TOIE2	= 6
+.equ	TICIE1	= 5
+.equ	OCIE1A	= 4
+.equ	OCIE1B	= 3
+.equ	TOIE1	= 2
+.equ	OCIE0	= 1
+.equ	TOIE0	= 0
+
+.equ	TICIE3	= 5		; ETIMSK
+.equ	OCIE3A	= 4
+.equ	OCIE3B	= 3
+.equ	TOIE3	= 2
+.equ	OCIE3C	= 1
+.equ	OCIE1C	= 0
+
+.equ	OCF2	= 7		; TIFR
+.equ	TOV2	= 6
+.equ	ICF1	= 5
+.equ	OCF1A	= 4
+.equ	OCF1B	= 3
+.equ	TOV1	= 2
+.equ	OCF0	= 1
+.equ	TOV0	= 0
+
+.equ	ICF3	= 5		; ETIFR
+.equ	OCF3A	= 4
+.equ	OCF3B	= 3
+.equ	TOV3	= 2
+.equ	OCF3C	= 1
+.equ	OCF1C	= 0
+
+;**** Asynchronous Timer ****
+.equ	AS0		= 3		; ASSR
+.equ	TCN0UB	= 2
+.equ	OCR0UB	= 1
+.equ	TCR0UB	= 0
+
+;**** Timer 0 ****
+.equ    FOC0    = 7		; TCCR0
+.equ	WGM00	= 6
+.equ	COM01	= 5
+.equ	COM00	= 4
+.equ	WGM01	= 3
+.equ	CS02	= 2
+.equ	CS01	= 1
+.equ	CS00	= 0
+
+;**** Timer 1 ****
+.equ	COM1A1	= 7		; TCCR1A
+.equ	COM1A0	= 6
+.equ	COM1B1	= 5
+.equ	COM1B0	= 4
+.equ	COM1C1	= 3
+.equ	COM1C0	= 2
+.equ	PWM11	= 1		; OBSOLETE! Use WGM11
+.equ	PWM10	= 0		; OBSOLETE! Use WGM10
+.equ	WGM11	= 1
+.equ	WGM10	= 0
+
+.equ	ICNC1	= 7		; TCCR1B
+.equ	ICES1	= 6
+.equ	CTC11	= 4		; OBSOLETE! Use WGM13
+.equ	CTC10	= 3		; OBSOLETE! Use WGM12
+.equ	WGM13	= 4
+.equ	WGM12	= 3
+.equ	CS12	= 2
+.equ	CS11	= 1
+.equ	CS10	= 0
+
+.equ	FOC1A	= 7		; TCCR1C
+.equ	FOC1B	= 6
+.equ	FOC1C	= 5
+
+;**** Timer 2 ****
+.equ	FOC2	= 7		; TCCR2
+.equ	WGM20	= 6
+.equ	COM21	= 5
+.equ	COM20	= 4
+.equ	WGM21	= 3
+.equ	CS22	= 2
+.equ	CS21	= 1
+.equ	CS20	= 0
+
+;**** Timer 3 ****
+.equ	COM3A1	= 7		; TCCR3A
+.equ	COM3A0	= 6
+.equ	COM3B1	= 5
+.equ	COM3B0	= 4
+.equ	COM3C1	= 3
+.equ	COM3C0	= 2
+.equ	PWM31	= 1		; OBSOLETE! Use WGM31
+.equ	PWM30	= 0		; OBSOLETE! Use WGM30
+.equ	WGM31	= 1
+.equ	WGM30	= 0
+
+.equ	ICNC3	= 7		; TCCR3B
+.equ	ICES3	= 6
+.equ	CTC31	= 4		; OBSOLETE! Use WGM33
+.equ	CTC30	= 3		; OBSOLETE! Use WGM32
+.equ	WGM33	= 4
+.equ	WGM32	= 3
+.equ	CS32	= 2
+.equ	CS31	= 1
+.equ	CS30	= 0
+
+.equ	FOC3A	= 7		; TCCR3C
+.equ	FOC3B	= 6
+.equ	FOC3C	= 5
+
+;**** Watchdog Timer ****
+.equ	WDCE	= 4		; WDTCR
+.equ	WDTOE	= 4		; For Mega103 compability
+.equ	WDE	= 3
+.equ	WDP2	= 2
+.equ	WDP1	= 1
+.equ	WDP0	= 0
+
+;**** EEPROM  Control Register ****
+.equ	EERIE	= 3		; EECR
+.equ	EEMWE	= 2
+.equ	EEWE	= 1
+.equ	EERE	= 0
+
+;**** USART 0 and USART 1 ****
+.equ	RXC	= 7		; (UCSRA0/1)
+.equ	TXC	= 6
+.equ	UDRE	= 5
+.equ	FE	= 4
+.equ	DOR	= 3
+.equ	PE	= 2		; OBSOLETED!
+.equ	U2X	= 1
+.equ	MPCM	= 0
+
+.equ	RXC0	= 7		; (UCSR0A)
+.equ	TXC0	= 6
+.equ	UDRE0	= 5
+.equ	FE0	= 4
+.equ	DOR0	= 3
+.equ	UPE0	= 2
+.equ	U2X0	= 1
+.equ	MPCM0	= 0
+
+.equ	RXC1	= 7		; (UCSR1A)
+.equ	TXC1	= 6
+.equ	UDRE1	= 5
+.equ	FE1	= 4
+.equ	DOR1	= 3
+.equ	UPE1	= 2
+.equ	U2X1	= 1
+.equ	MPCM1	= 0
+
+.equ	RXCIE	= 7		; (UCSRB0/1)
+.equ	TXCIE	= 6
+.equ	UDRIE	= 5
+.equ	RXEN	= 4
+.equ	TXEN	= 3
+.equ	UCSZ2	= 2
+.equ	RXB8	= 1
+.equ	TXB8	= 0
+
+.equ	RXCIE0	= 7		; (UCSR0B)
+.equ	TXCIE0	= 6
+.equ	UDRIE0	= 5
+.equ	RXEN0	= 4
+.equ	TXEN0	= 3
+.equ	UCSZ02	= 2
+.equ	RXB80	= 1
+.equ	TXB80	= 0
+
+.equ	RXCIE1	= 7		; (UCSR1B)
+.equ	TXCIE1	= 6
+.equ	UDRIE1	= 5
+.equ	RXEN1	= 4
+.equ	TXEN1	= 3
+.equ	UCSZ12	= 2
+.equ	RXB81	= 1
+.equ	TXB81	= 0
+
+.equ	UMSEL	= 6		; (UCSRC0/1)
+.equ	UPM1	= 5
+.equ	UPM0	= 4
+.equ	USBS	= 3
+.equ	UCSZ1	= 2
+.equ	UCSZ0	= 1
+.equ	UCPOL	= 0
+
+.equ	UMSEL0	= 6		; (UCSR0C)
+.equ	UPM01	= 5
+.equ	UPM00	= 4
+.equ	USBS0	= 3
+.equ	UCSZ01	= 2
+.equ	UCSZ00	= 1
+.equ	UCPOL0	= 0
+
+.equ	UMSEL1	= 6		; (UCSR1C)
+.equ	UPM11	= 5
+.equ	UPM10	= 4
+.equ	USBS1	= 3
+.equ	UCSZ11	= 2
+.equ	UCSZ10	= 1
+.equ	UCPOL1	= 0
+
+	
+;**** SPI ****
+.equ	SPIE	= 7		; SPCR
+.equ	SPE	= 6
+.equ	DORD	= 5
+.equ	MSTR	= 4
+.equ	CPOL	= 3
+.equ	CPHA	= 2
+.equ	SPR1	= 1
+.equ	SPR0	= 0
+
+.equ	SPIF	= 7		; SPSR
+.equ	WCOL	= 6
+.equ	SPI2X	= 0
+
+;**** TWI ****	
+.equ	TWINT	= 7		;TWCR
+.equ	TWEA	= 6
+.equ	TWSTA	= 5
+.equ	TWSTO	= 4
+.equ	TWWC	= 3
+.equ    TWEN    = 2
+.equ	TWIE	= 0
+
+.equ	TWS7	= 7		; TWSR
+.equ	TWS6	= 6
+.equ	TWS5	= 5
+.equ	TWS4	= 4
+.equ	TWS3	= 3
+.equ	TWPS1	= 1
+.equ	TWPS0	= 0
+
+.equ	TWA6	= 7
+.equ	TWA5	= 6
+.equ	TWA4	= 5
+.equ	TWA3	= 4
+.equ	TWA2	= 3
+.equ	TWA1	= 2
+.equ	TWA0	= 1
+.equ	TWGCE	= 0		; TWAR
+
+		
+;**** PORT A ****
+.equ	PA7	= 7		; PORTA
+.equ	PA6	= 6
+.equ	PA5	= 5
+.equ	PA4	= 4
+.equ	PA3	= 3
+.equ	PA2	= 2
+.equ	PA1	= 1
+.equ	PA0	= 0
+.equ	PORTA7	= 7
+.equ	PORTA6	= 6
+.equ	PORTA5	= 5
+.equ	PORTA4	= 4
+.equ	PORTA3	= 3
+.equ	PORTA2	= 2
+.equ	PORTA1	= 1
+.equ	PORTA0	= 0
+
+.equ	DDA7	= 7		; DDRA
+.equ	DDA6	= 6
+.equ	DDA5	= 5
+.equ	DDA4	= 4
+.equ	DDA3	= 3
+.equ	DDA2	= 2
+.equ	DDA1	= 1
+.equ	DDA0	= 0
+
+.equ	PINA7	= 7		; PINA
+.equ	PINA6	= 6
+.equ	PINA5	= 5
+.equ	PINA4	= 4
+.equ	PINA3	= 3
+.equ	PINA2	= 2
+.equ	PINA1	= 1
+.equ	PINA0	= 0
+
+;**** PORT B ****
+.equ	PB7	= 7		; PORTB
+.equ	PB6	= 6
+.equ	PB5	= 5
+.equ	PB4	= 4
+.equ	PB3	= 3
+.equ	PB2	= 2
+.equ	PB1	= 1
+.equ	PB0	= 0
+.equ	PORTB7	= 7
+.equ	PORTB6	= 6
+.equ	PORTB5	= 5
+.equ	PORTB4	= 4
+.equ	PORTB3	= 3
+.equ	PORTB2	= 2
+.equ	PORTB1	= 1
+.equ	PORTB0	= 0
+
+.equ	DDB7	= 7		; DDRB
+.equ	DDB6	= 6
+.equ	DDB5	= 5
+.equ	DDB4	= 4
+.equ	DDB3	= 3
+.equ	DDB2	= 2
+.equ	DDB1	= 1
+.equ	DDB0	= 0
+
+.equ	PINB7	= 7		; PINB
+.equ	PINB6	= 6
+.equ	PINB5	= 5
+.equ	PINB4	= 4
+.equ	PINB3	= 3
+.equ	PINB2	= 2
+.equ	PINB1	= 1
+.equ	PINB0	= 0
+
+;**** PORT C ****
+.equ	PC7	= 7		; PORTC
+.equ	PC6	= 6
+.equ	PC5	= 5
+.equ	PC4	= 4
+.equ	PC3	= 3
+.equ	PC2	= 2
+.equ	PC1	= 1
+.equ	PC0	= 0
+.equ	PORTC7	= 7
+.equ	PORTC6	= 6
+.equ	PORTC5	= 5
+.equ	PORTC4	= 4
+.equ	PORTC3	= 3
+.equ	PORTC2	= 2
+.equ	PORTC1	= 1
+.equ	PORTC0	= 0
+
+.equ	DDC7	= 7		; DDRC
+.equ	DDC6	= 6
+.equ	DDC5	= 5
+.equ	DDC4	= 4
+.equ	DDC3	= 3
+.equ	DDC2	= 2
+.equ	DDC1	= 1
+.equ	DDC0	= 0
+
+.equ	PINC7	= 7		; PINC
+.equ	PINC6	= 6
+.equ	PINC5	= 5
+.equ	PINC4	= 4
+.equ	PINC3	= 3
+.equ	PINC2	= 2
+.equ	PINC1	= 1
+.equ	PINC0	= 0
+
+;**** PORT D ****
+.equ	PD7	= 7		; PORTD
+.equ	PD6	= 6
+.equ	PD5	= 5
+.equ	PD4	= 4
+.equ	PD3	= 3
+.equ	PD2	= 2
+.equ	PD1	= 1
+.equ	PD0	= 0
+.equ	PORTD7	= 7
+.equ	PORTD6	= 6
+.equ	PORTD5	= 5
+.equ	PORTD4	= 4
+.equ	PORTD3	= 3
+.equ	PORTD2	= 2
+.equ	PORTD1	= 1
+.equ	PORTD0	= 0
+
+.equ	DDD7	= 7		; DDRD
+.equ	DDD6	= 6
+.equ	DDD5	= 5
+.equ	DDD4	= 4
+.equ	DDD3	= 3
+.equ	DDD2	= 2
+.equ	DDD1	= 1
+.equ	DDD0	= 0
+
+.equ	PIND7	= 7		; PIND
+.equ	PIND6	= 6
+.equ	PIND5	= 5
+.equ	PIND4	= 4
+.equ	PIND3	= 3
+.equ	PIND2	= 2
+.equ	PIND1	= 1
+.equ	PIND0	= 0
+
+;**** PORT E ****
+.equ	PE7	= 7		; PORTE
+.equ	PE6	= 6
+.equ	PE5	= 5
+.equ	PE4	= 4
+.equ	PE3	= 3
+.equ	PE2	= 2
+.equ	PE1	= 1
+.equ	PE0	= 0
+.equ	PORTE7	= 7		; PORTE
+.equ	PORTE6	= 6
+.equ	PORTE5	= 5
+.equ	PORTE4	= 4
+.equ	PORTE3	= 3
+.equ	PORTE2	= 2
+.equ	PORTE1	= 1
+.equ	PORTE0	= 0
+
+.equ	DDE7	= 7		; DDRE
+.equ	DDE6	= 6
+.equ	DDE5	= 5
+.equ	DDE4	= 4
+.equ	DDE3	= 3
+.equ	DDE2	= 2
+.equ	DDE1	= 1
+.equ	DDE0	= 0
+
+.equ	PINE7	= 7		; PINE
+.equ	PINE6	= 6
+.equ	PINE5	= 5
+.equ	PINE4	= 4
+.equ	PINE3	= 3
+.equ	PINE2	= 2
+.equ	PINE1	= 1
+.equ	PINE0	= 0
+
+;**** PORT F ****
+.equ	PF7	= 7		; PORTF
+.equ	PF6	= 6
+.equ	PF5	= 5
+.equ	PF4	= 4
+.equ	PF3	= 3
+.equ	PF2	= 2
+.equ	PF1	= 1
+.equ	PF0	= 0
+.equ	PORTF7	= 7
+.equ	PORTF6	= 6
+.equ	PORTF5	= 5
+.equ	PORTF4	= 4
+.equ	PORTF3	= 3
+.equ	PORTF2	= 2
+.equ	PORTF1	= 1
+.equ	PORTF0	= 0
+
+.equ	DDF7	= 7		; DDRF
+.equ	DDF6	= 6
+.equ	DDF5	= 5
+.equ	DDF4	= 4
+.equ	DDF3	= 3
+.equ	DDF2	= 2
+.equ	DDF1	= 1
+.equ	DDF0	= 0
+
+.equ	PINF7	= 7		; PINF
+.equ	PINF6	= 6
+.equ	PINF5	= 5
+.equ	PINF4	= 4
+.equ	PINF3	= 3
+.equ	PINF2	= 2
+.equ	PINF1	= 1
+.equ	PINF0	= 0
+
+;**** PORT G ****
+.equ	PG4	= 4		; PORTG
+.equ	PG3	= 3
+.equ	PG2	= 2
+.equ	PG1	= 1
+.equ	PG0	= 0
+
+.equ	DDG4	= 4		; DDRG
+.equ	DDG3	= 3
+.equ	DDG2	= 2
+.equ	DDG1	= 1
+.equ	DDG0	= 0
+
+.equ	PING4	= 4		; PING
+.equ	PING3	= 3
+.equ	PING2	= 2
+.equ	PING1	= 1
+.equ	PING0	= 0
+
+
+;*****************************************************************************
+; CPU Register Declarations
+;*****************************************************************************
+
+.def	XL	= r26		; X pointer low
+.def	XH	= r27		; X pointer high
+.def	YL	= r28		; Y pointer low
+.def	YH	= r29		; Y pointer high
+.def	ZL	= r30		; Z pointer low
+.def	ZH	= r31		; Z pointer high
+
+
+;*****************************************************************************
+; Data Memory Declarations
+;*****************************************************************************
+
+.equ 	RAMEND	= $10ff		; Highest internal data memory (SRAM) address.
+.equ	EEPROMEND = $0fff       ; Highest EEPROM address.
+	
+;*****************************************************************************
+; Program Memory Declarations
+;*****************************************************************************
+
+.equ    FLASHEND = $FFFF	;  Highest program memory (flash) address
+	                        ; (When addressed as 16 bit words)
+		
+;**** Boot Vectors ****
+			 ;  byte groups
+			 ;  /--\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	= 0b1111111000000000	; ($FE00) Smallest boot block is 512W
+.equ 	SECONDBOOTSTART	= 0b1111110000000000	; ($FC00) 2'nd boot block size is 1KW
+.equ 	THIRDBOOTSTART	= 0b1111100000000000	; ($F800) Third boot block size is 2KW
+.equ 	LARGEBOOTSTART	= 0b1111000000000000	; ($F000) Largest boot block is 4KW
+
+
+;**** Page Size ****
+.equ	PAGESIZE	= 128	; Number of WORDS in a page
+
+
+;**** Interrupt Vectors ****
+.equ	INT0addr  = $002	; External Interrupt0 Vector Address
+.equ	INT1addr  = $004	; External Interrupt1 Vector Address
+.equ	INT2addr  = $006	; External Interrupt2 Vector Address
+.equ	INT3addr  = $008	; External Interrupt3 Vector Address
+.equ	INT4addr  = $00a	; External Interrupt4 Vector Address
+.equ	INT5addr  = $00c	; External Interrupt5 Vector Address
+.equ	INT6addr  = $00e	; External Interrupt6 Vector Address
+.equ	INT7addr  = $010	; External Interrupt7 Vector Address
+.equ	OC2addr   = $012	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr  = $014	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr  = $016	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr  = $018	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr  = $01a	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr  = $01c	; Overflow1 Interrupt Vector Address
+.equ	OC0addr   = $01e	; Output Compare0 Interrupt Vector Address
+.equ	OVF0addr  = $020	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr   = $022	; SPI Interrupt Vector Address
+.equ	URXC0addr = $024	; USART0 Receive Complete Interrupt Vector Address
+.equ	UDRE0addr = $026	; USART0 Data Register Empty Interrupt Vector Address
+.equ	UTXC0addr = $028	; USART0 Transmit Complete Interrupt Vector Address
+.equ    ADCCaddr  = $02a	; ADC Conversion Complete Handle
+.equ	ERDYaddr  = $02c	; EEPROM Write Complete Handle
+.equ	ACIaddr   = $02e	; Analog Comparator Interrupt Vector Address
+
+.equ	OC1Caddr  = $030	; Output Compare1C Interrupt Vector Address
+.equ	ICP3addr  = $032	; Input Capture3 Interrupt Vector Address
+.equ	OC3Aaddr  = $034	; Output Compare3A Interrupt Vector Address
+.equ	OC3Baddr  = $036	; Output Compare3B Interrupt Vector Address
+.equ	OC3Caddr  = $038	; Output Compare3C Interrupt Vector Address
+.equ	OVF3addr  = $03A	; Overflow3 Interrupt Vector Address
+.equ	URXC1addr = $03C	; USART1 Receive Complete Interrupt Vector Address
+.equ	UDRE1addr = $03E	; USART1 Data Register Empty Interrupt Vector Address
+.equ	UTXC1addr = $040	; USART1 Transmit Complete Interrupt Vector Address
+.equ    TWIaddr   = $042	; TWI Interrupt Vector Address
+.equ	SPMRaddr  = $044	; Store Program Memory Ready Interrupt Vector Address
+
+
+;**** End of File ****
diff --git a/include/m161def.inc b/include/m161def.inc
new file mode 100644
index 0000000..f7701b6
--- /dev/null
+++ b/include/m161def.inc
@@ -0,0 +1,494 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		        :AVR000
+;* File Name		    :"m161def.inc"
+;* Title		        :Register/Bit Definitions for the ATmega161
+;* Date                 :00.12.12
+;* Version              :
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax		    :+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail	    :avr@atmel.no
+;* Target MCU		    :ATmega161
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega161
+
+;***** I/O Register Definitions
+.equ SREG =$3f
+.equ SPH =$3e
+.equ SPL =$3d
+.equ GIMSK =$3b
+.equ GIFR =$3a
+.equ TIMSK =$39
+.equ TIFR =$38
+.equ SPMCR =$37
+.equ EMCUCR =$36
+.equ MCUCR =$35
+.equ MCUSR   =$34
+.equ TCCR0 =$33
+.equ TCNT0 =$32
+.equ OCR0 =$31
+.equ SFIOR =$30
+.equ TCCR1A =$2f
+.equ TCCR1B =$2e
+.equ TCNT1H =$2d
+.equ TCNT1L =$2c
+.equ OCR1AH =$2b
+.equ OCR1AL =$2a
+.equ OCR1BH =$29
+.equ OCR1BL =$28
+.equ TCCR2 =$27
+.equ ASSR    =$26
+.equ ICR1H =$25
+.equ ICR1L =$24
+.equ TCNT2 =$23
+.equ OCR2 =$22
+.equ WDTCR =$21
+.equ UBRRHI  =$20
+.equ EEARH =$1f
+.equ EEARL =$1e
+.equ EEDR =$1d
+.equ EECR =$1c
+.equ PORTA =$1b
+.equ DDRA =$1a
+.equ PINA =$19
+.equ PORTB =$18
+.equ DDRB =$17
+.equ PINB =$16
+.equ PORTC =$15
+.equ DDRC =$14
+.equ PINC =$13
+.equ PORTD =$12
+.equ DDRD =$11
+.equ PIND =$10
+.equ SPDR =$0f
+.equ SPSR =$0e
+.equ SPCR =$0d
+.equ UDR0 =$0c
+.equ UDR =$0c       ;for compatibility with s8515
+.equ UCSR0A =$0b
+.equ USR =$0b       ;for compatibility with s8515
+.equ UCSR0B =$0a
+.equ UCR =$0a ;for compatibility with s8515
+.equ UBRR0 =$09
+.equ UBRR =$09 ;for compatibility with s8515
+.equ ACSR =$08
+.equ PORTE =$07
+.equ DDRE =$06
+.equ PINE =$05
+.equ UDR1 =$03
+.equ UCSR1A =$02
+.equ UCSR1B =$01
+.equ UBRR1 =$00
+
+
+;***** Bit Definitions
+
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+
+;TIMSK
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ	TOIE2	=4
+.equ	TICIE1	=3
+.equ	OCIE2	=2
+.equ	TOIE0	=1
+.equ	OCIE0	=0
+
+;TIFR
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	TOV2	=4
+.equ	ICF1	=3
+.equ	OCF2	=2
+.equ	TOV0	=1
+.equ	OCF0	=0
+
+;SPMCR
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;EMCUCR
+.equ	SM0	=7
+.equ	SRL2	=6
+.equ	SRL1	=5
+.equ	SRL0	=4
+.equ	SRW01	=3
+.equ	SRW00	=2
+.equ	SRW11	=1
+.equ	ISC2	=0
+
+;MCUCR
+.equ	SRE	=7
+.equ	SRW	=6 ;for compatibility with s8515
+.equ	SRW10	=6
+.equ	SE	=5
+.equ	SM	=4 ;for compatibility with s8515
+.equ	SM1	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;TCCR0
+.equ	FOC0	=7
+.equ	PWM0	=6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	CTC0	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;SFIOR
+.equ	PSR10	=0
+.equ	PSR2	=1
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	FOC2	=7
+.equ	PWM2	=6
+.equ	COM21	=5
+.equ	COM20	=4
+.equ	CTC2	=3
+.equ	CS22	=2
+.equ	CS21	=1
+.equ	CS20	=0
+
+;ASSR
+.equ	AS2	=3
+.equ	TCN2UB	=2
+.equ	OCR2UB	=1
+.equ	TCR2UB	=0
+
+;WDTCR
+.equ	WDDE	=4	
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ	EERIE	=3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;PORTE
+.equ	PE2	=2
+.equ	PE1	=1
+.equ	PE0	=0
+
+;DDRE
+.equ	DDE2	=2
+.equ	DDE1	=1
+.equ	DDE0	=0
+
+;PINE
+.equ	PINE2	=2
+.equ	PINE1	=1
+.equ	PINE0	=0
+
+; USR (for compatibility with s8515)
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3
+.equ	U2X	=1
+
+;UCSR0A
+.equ	RXC0	=7
+.equ	TXC0	=6
+.equ	UDRE0	=5
+.equ	FE0	=4
+.equ	OR0	=3
+.equ	U2X0	=1
+.equ	MPCM0	=0
+
+;UCSR1A
+.equ	RXC1	=7
+.equ	TXC1	=6
+.equ	UDRE1	=5
+.equ	FE1	=4
+.equ	OR1	=3
+.equ	U2X1	=1
+.equ	MPCM1	=0
+
+; SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+; SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+; UCR (for compatibility with s8515)
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+; UCSR0B
+.equ	RXCIE0	=7
+.equ	TXCIE0	=6
+.equ	UDRIE0	=5
+.equ	RXEN0	=4
+.equ	TXEN0	=3
+.equ	CHR90	=2
+.equ	RXB80	=1
+.equ	TXB80	=0
+
+;	UCSR1B
+.equ	RXCIE1	=7
+.equ	TXCIE1	=6
+.equ	UDRIE1	=5
+.equ	RXEN1	=4
+.equ	TXEN1	=3
+.equ	CHR91	=2
+.equ	RXB81	=1
+.equ	TXB81	=0
+
+;ACSR
+.equ	ACD	=7
+.equ	AINBG	=6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+; Boot loader Lock bit
+.equ	BLB12	=5
+.equ	BLB11	=4
+.equ	BLB02	=3
+.equ	BLB01	=2
+
+;X,Y,Z pointer
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	FLASHEND	=$1FFF
+.equ 	E2END	    =$1FF
+.equ	RAMEND	    =$45F
+.equ	XRAMEND	    =$FFFF
+
+.equ	BOOTSTART	=$1E00
+
+.equ	INT0addr	=$002	;External	Interrupt0 Vector Address
+.equ	INT1addr	=$004	;External Interrupt1 Vector Address
+.equ	INT2addr	=$006	;External Interrupt1 Vector Address
+.equ	CMP2addr	=$008	;Input Capture1 Interrupt Vector Address
+.equ	OVF2addr	=$00a	;Overflow1 Interrupt Vector Address
+.equ	ICP1addr	=$00c	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr	=$00e	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr	=$010	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr	=$012	;Overflow1 Interrupt Vector Address
+.equ	CMP0addr	=$014	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr	=$016	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr		=$018	;SPI Interrupt Vector Address
+.equ	URXC0addr	=$01a	;UART Receive Complete Interrupt Vector Address
+.equ	URXC1addr	=$01c	;UART Receive Complete Interrupt Vector Address
+.equ	UDRE0addr	=$01e	;UART Data Register Empty Interrupt Vector Address
+.equ	UDRE1addr	=$020	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXC0addr	=$022	;UART Transmit Complete Interrupt Vector Address
+.equ	UTXC1addr	=$024	;UART Transmit Complete Interrupt Vector Address
+.equ	EERDYaddr	=$026	;UART Transmit Complete Interrupt Vector Address
+.equ	ACIaddr		=$028	;Analog Comparator Interrupt Vector Address
+
+;for compatibility with s8515
+.equ	URXCaddr	=$01a	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr	=$01e	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr	=$022	;UART Transmit Complete Interrupt Vector Address
diff --git a/include/m162def.inc b/include/m162def.inc
new file mode 100644
index 0000000..3359c1a
--- /dev/null
+++ b/include/m162def.inc
@@ -0,0 +1,678 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"m162def.inc"
+;* Title				:Register/Bit Definitions for the ATmega162
+;* Date                 :2001.09.19
+;* Version              :1.00
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.no
+;* Target MCU			:ATmega162
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega162
+	
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
+;**** Not available in Mega162 compatibility mode      ****
+.equ	TCCR3A	=$8b
+.equ	TCCR3B	=$8a	
+.equ	TCNT3H	=$89
+.equ	TCNT3L	=$88
+.equ	OCR3AH	=$87
+.equ	OCR3AL	=$86	
+.equ	OCR3BH	=$85
+.equ	OCR3BL	=$84
+.equ	ICR3H	=$81
+.equ	ICR3L	=$80
+.equ	ETIMSK  =$7d
+.equ	ETIFR	=$7c
+.equ	PCMSK1	=$6c
+.equ	PCMSK0	=$6b
+.equ	CLKPR	=$61	
+				
+;***** I/O Register Definitions	
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	UCSR1C	=$3c		; Note! UCSR1C equals UBRR1H
+.equ	UBRR1H	=$3c		; Note! UCSR1C equals UBRR1H
+.equ	EIMSK	=$3b	
+.equ	GIMSK	=$3b
+.equ	GICR	=$3b		; new name for GIMSK
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ	EMCUCR	=$36
+.equ	MCUCR	=$35
+.equ    MCUSR   =$34		; For compatibility, 
+.equ    MCUCSR  =$34		; keep both names until further	
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	OCR0	=$31
+.equ	SFIOR	=$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	TCCR2	=$27
+.equ    ASSR    =$26
+.equ	ICR1H	=$25
+.equ	ICR1L	=$24
+.equ	TCNT2	=$23
+.equ	OCR2	=$22
+.equ	WDTCR	=$21
+.equ    UBRRHI  =$20		; Old ATmega161
+.equ	UCSR0C	=$20		; Note! UCSR0C equals UBRR0H
+.equ	UBRR0H	=$20		; Note! UCSR0C equals UBRR0H		
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR0	=$0c
+.equ	UDR		=$0c		;for compatibility with s8515
+.equ	UCSR0A	=$0b
+.equ	USR		=$0b		;for compatibility with s8515
+.equ	UCSR0B	=$0a
+.equ	UCR		=$0a		;for compatibility with s8515
+.equ	UBRR0	=$09		;Old mega161
+.equ	UBRR0L	=$09	
+.equ	UBRR	=$09		;for compatibility with s8515
+.equ	ACSR	=$08
+.equ	PORTE	=$07
+.equ	DDRE	=$06
+.equ	PINE	=$05
+.equ	OSCCAL	=$04		; New
+.equ	UDR1	=$03
+.equ	UCSR1A	=$02
+.equ	UCSR1B	=$01
+.equ	UBRR1	=$00		;Old mega161
+.equ	UBRR1L	=$00
+
+;***** Bit Definitions
+;TCCR3A
+.equ	COM3A1	=7
+.equ	COM3A0	=6
+.equ	COM3B1	=5
+.equ	COM3B0	=4
+.equ	FOC3A	=3
+.equ	FOC3B	=2
+.equ	WGM31	=1
+.equ	WGM30	=0
+
+;TCCR3A
+.equ	ICNC3	=7
+.equ	ICES3	=6
+.equ	WGM33	=4
+.equ	WGM32	=3
+.equ	CS32	=2
+.equ	CS31	=1
+.equ	CS30	=0
+
+;ETIMSK
+.equ	TICIE3	=5
+.equ	OCIE3A	=4
+.equ	OCIE3B	=3
+.equ	TOIE3	=2
+					 
+;ETIFR
+.equ	ICF3	=5
+.equ	OCF3A	=4
+.equ	OCF3B	=3
+.equ	TOV3	=2
+
+;PCMSK1
+.equ	PCINT15	=7
+.equ	PCINT14	=6
+.equ	PCINT13	=5
+.equ    PCINT12	=4	
+.equ	PCINT11	=3
+.equ    PCINT10	=2	
+.equ	PCINT9	=1
+.equ	PCINT8	=0
+	
+;PCMSK1
+.equ	PCINT7  =7
+.equ	PCINT6  =6
+.equ	PCINT5  =5
+.equ    PCINT4  =4	
+.equ	PCINT3 	=3
+.equ    PCINT2 	=2	
+.equ	PCINT1	=1
+.equ	PCINT0  =0
+
+;CLKPR
+.equ	CLKPCE  =7
+.equ	CLKPS3 	=3
+.equ    CLKPS2 	=2	
+.equ	CLKPS1	=1
+.equ	CLKPS0  =0
+			
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+.equ	PCIE1 	=4
+.equ    PCIE0 	=3		
+.equ	IVSEL	=1		; Interrupt vector select
+.equ	IVCE	=0		; Interrupt vector change enable
+	
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+.equ	PCIF1	=4
+.equ	PCIF0	=3	
+	
+	
+;TIMSK
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ    OCIE2   =4
+.equ	TICIE1	=3
+.equ    TOIE2   =2
+.equ	TOIE0	=1
+.equ	OCIE0	=0
+
+;TIFR
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	OCF2	=4
+.equ	ICF1	=3
+.equ	TOV2	=2
+.equ	TOV0	=1
+.equ	OCF0	=0
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	RWWSB	=6
+.equ	ASB	=6			; old
+.equ	RWWSRE	=4
+.equ	ASRE	=4		; old
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;EMCUCR
+.equ    SM0     =7
+.equ	SRL2	=6
+.equ	SRL1	=5
+.equ	SRL0	=4
+.equ	SRW01	=3
+.equ	SRW00	=2
+.equ	SRW11	=1
+.equ	ISC2	=0
+
+;MCUCR
+.equ	SRE		=7
+.equ	SRW		=6		;for compatibility with s8515
+.equ	SRW10	=6
+.equ	SE		=5
+.equ	SM		=4		;for compatibility with s8515
+.equ	SM1		=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;MCUSR
+.equ	JTD     =7	
+.equ	SM2     =5	
+.equ    JTRF    =4	
+.equ	WDRF	=3
+.equ	BORF	=2
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+;TCCR0
+.equ    FOC0    =7
+.equ	WGM00	=6
+.equ    PWM0    =6		; OBSOLETE! Use WGM00
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	WGM01	=3
+.equ	CTC0	=3		; OBSOLETE! Use WGM01
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;SFIOR
+.equ	TSM		= 7
+.equ	XMBK	= 6		; Added for Mega162
+.equ	XMM2	= 5
+.equ	XMM1	= 4
+.equ	XMM0	= 3
+.equ	PUD		= 2
+.equ    PSR2    = 1
+.equ    PSR10   = 0		; Note:	The prescaler reset is shared
+						; between timer 0 and 1.
+.equ    PSR1	= 0
+.equ    PSR0	= 0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ    FOC1A   =3
+.equ    FOC1B   =2
+.equ	PWM11	=1		; OBSOLETE! Use WGM11
+.equ	WGM11	=1
+.equ	PWM10	=0		; OBSOLETE! Use WGM10
+.equ	WGM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC11	=4		; OBSOLETE! Use WGM13
+.equ	WGM13	=4
+.equ	CTC10	=3		; OBSOLETE! Use WGM12
+.equ	WGM12	=3
+.equ	CTC1	=3		; Old Mega161
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ    FOC2    =7
+.equ	WGM20	=6
+.equ    PWM2    =6		; OBSOLETE! Use WGM20
+.equ	COM21	=5
+.equ	COM20	=4
+.equ	WGM21	=3
+.equ	CTC2	=3		; OBSOLETE! Use WGM21
+.equ	CS22	=2
+.equ	CS21	=1
+.equ	CS20	=0
+
+;ASSR
+.equ	AS2	=3
+.equ	TCN2UB	=2
+.equ	OCR2UB	=1
+.equ	TCR2UB	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDCE	=4		; Added for Mega161B
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PORTA7	=7
+.equ	PORTA6	=6
+.equ	PORTA5	=5
+.equ	PORTA4	=4
+.equ	PORTA3	=3
+.equ	PORTA2	=2
+.equ	PORTA1	=1
+.equ	PORTA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PORTB7	=7
+.equ	PORTB6	=6
+.equ	PORTB5	=5
+.equ	PORTB4	=4
+.equ	PORTB3	=3
+.equ	PORTB2	=2
+.equ	PORTB1	=1
+.equ	PORTB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PORTC7	=7
+.equ	PORTC6	=6
+.equ	PORTC5	=5
+.equ	PORTC4	=4
+.equ	PORTC3	=3
+.equ	PORTC2	=2
+.equ	PORTC1	=1
+.equ	PORTC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PORTD7	=7
+.equ	PORTD6	=6
+.equ	PORTD5	=5
+.equ	PORTD4	=4
+.equ	PORTD3	=3
+.equ	PORTD2	=2
+.equ	PORTD1	=1
+.equ	PORTD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;PORTE
+.equ	PORTE2	=2
+.equ	PORTE1	=1
+.equ	PORTE0	=0
+
+;DDRE
+.equ	DDE2	=2
+.equ	DDE1	=1
+.equ	DDE0	=0
+
+;PINE
+.equ	PINE2	=2
+.equ	PINE1	=1
+.equ	PINE0	=0
+
+;USR (for compatibility with s8515)
+.equ	RXC		=7
+.equ	TXC		=6
+.equ	UDRE	=5
+.equ	FE		=4
+.equ	OR		=3
+.equ	U2X		=1
+
+;UCSR0A
+.equ	RXC0	=7
+.equ	TXC0	=6
+.equ	UDRE0	=5
+.equ	FE0		=4
+.equ	OR0		=3		; Old name kept for compatibilty
+.equ	DOR0	=3
+.equ	PE0		=2		; New
+.equ	U2X0	=1
+.equ	MPCM0	=0
+
+;UCSR1A
+.equ	RXC1	=7
+.equ	TXC1	=6
+.equ	UDRE1	=5
+.equ	FE1		=4
+.equ	OR1		=3		; Old name kept for compatibilty
+.equ	DOR1	=3
+.equ	PE1		=2		; New
+.equ	U2X1	=1
+.equ	MPCM1	=0
+
+;SPCR
+.equ	SPIE	=7
+.equ	SPE		=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;UCR (for compatibility with s8515)
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; Old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+; UCSR0B
+.equ	RXCIE0	=7
+.equ	TXCIE0	=6
+.equ	UDRIE0	=5
+.equ	RXEN0	=4
+.equ	TXEN0	=3
+.equ	CHR90	=2		; Old name kept for compatibilty
+.equ	UCSZ02	=2
+.equ	RXB80	=1
+.equ	TXB80	=0
+
+; UCSR1B
+.equ	RXCIE1	=7
+.equ	TXCIE1	=6
+.equ	UDRIE1	=5
+.equ	RXEN1	=4
+.equ	TXEN1	=3
+.equ	CHR91	=2		; Old name kept for compatibilty
+.equ	UCSZ12	=2
+.equ	RXB81	=1
+.equ	TXB81	=0
+	
+;UCSR0C					New 
+.equ	URSEL0	=7
+.equ	UMSEL0	=6
+.equ	UPM01	=5
+.equ	UPM00	=4
+.equ	USBS0	=3
+.equ	UCSZ01	=2
+.equ	UCSZ00	=1
+.equ	UCPOL0	=0
+
+;UCSR1C					New 
+.equ	URSEL1	=7
+.equ	UMSEL1	=6
+.equ	UPM11	=5
+.equ	UPM10	=4
+.equ	USBS1	=3
+.equ	UCSZ11	=2
+.equ	UCSZ10	=1
+.equ	UCPOL1	=0
+	
+
+;ACSR
+.equ	ACD		=7
+.equ	AINBG	=6		; Old mega161
+.equ	ACBG	=6	
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+
+
+; Boot loader Lock bit
+.equ	BLB12	=5
+.equ	BLB11	=4
+.equ	BLB02	=3
+.equ	BLB01	=2
+
+;*****************************************************************************
+; CPU Register Declarations
+;*****************************************************************************
+
+.def	XL		= r26		; X pointer low
+.def	XH		= r27		; X pointer high
+.def	YL		= r28		; Y pointer low
+.def	YH		= r29		; Y pointer high
+.def	ZL		= r30		; Z pointer low
+.def	ZH		= r31		; Z pointer high
+
+
+;*****************************************************************************
+; Data Memory Declarations
+;*****************************************************************************
+
+.equ 	RAMEND	= $488		; Highest internal data memory (SRAM) address.
+							;(1k RAM + IO + REG)
+.equ	EEPROMEND = $01ff   ; Highest EEPROM address.
+	                        ;(512 byte)
+;*****************************************************************************
+; Program Memory Declarations
+;*****************************************************************************
+
+.equ    FLASHEND = $1FFF	;  Highest program memory (flash) address
+	                        ; (When addressed as 16 bit words)
+							; ( 8k words , 16k byte ) 
+		
+;**** Boot Vectors ****
+					   ;  byte groups
+					 ;   /--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b1111110000000  ;($1F80) smallest boot block is 256B
+.equ 	SECONDBOOTSTART	=0b1111100000000  ;($1F00) second boot block size is 512B
+.equ 	THIRDBOOTSTART	=0b1111000000000  ;($1E00) third boot block size is 1KB
+.equ 	LARGEBOOTSTART	=0b1110000000000  ;($1C00) largest boot block is 2KB
+.equ 	BOOTSTART	=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+
+
+
+.equ	INT0addr		= $002	;	External Interrupt Request 0
+.equ	INT1addr		= $004	;	External Interrupt Request 1
+.equ	INT2addr		= $006	;	External Interrupt Request 2
+.equ	PCINT0addr		= $008	;	Pin Change Interrupt Request 0
+.equ	PCINT1addr		= $00A
+.equ	TIMER3CAPTaddr	= $00C
+.equ	TIMER3COMPAaddr	= $00E
+.equ	TIMER3COMPBaddr	= $010
+.equ	TIMER3OVFaddr	= $012
+.equ	TIMER2COMPaddr	= $014
+.equ	TIMER2OVFaddr	= $016
+.equ	TIMER1CAPTaddr	= $018
+.equ	TIMER1COMPAaddr	= $01A
+.equ	TIMER1COMPBaddr	= $01C
+.equ	TIMER1OVFaddr	= $01E
+.equ	TIMER0COMPaddr	= $020
+.equ	TIMER0OVFaddr	= $022
+.equ	SPISTCaddr		= $024
+.equ	USART0RXCaddr	= $026
+.equ	USART1RXCaddr	= $028
+.equ	USART0UDREaddr	= $02A
+.equ	USART1UDREaddr	= $02C
+.equ	USART0TXCaddr	= $02E
+.equ	USART1TXCaddr	= $030
+.equ	EE_RDYaddr		= $032
+.equ	ANA_CMPaddr		= $034
+.equ	SPM_RDYaddr		= $036
diff --git a/include/m163def.inc b/include/m163def.inc
new file mode 100644
index 0000000..b45bca7
--- /dev/null
+++ b/include/m163def.inc
@@ -0,0 +1,454 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		        :AVR000
+;* File Name		    :"m163def.inc"
+;* Title		        :Register/Bit Definitions for the ATmega163
+;* Date                 :00.12.12
+;* Version              :
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax		    :+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail	    :avr@atmel.no
+;* Target MCU		    :ATmega163
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega163
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH	    =$3e
+.equ	SPL	    =$3d
+.equ	GIMSK	=$3b
+.equ	GICR	=$3b		; new name for GIMSK	
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRHI  =$20
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	    =$0c
+.equ	UCSRA	=$0b
+.equ	USR	    =$0b    ; For compatibility with S8535
+.equ	UCSRB	=$0a
+.equ	UCR	    =$0a    ; For compatibility with S8535
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+
+;***** Bit Definitions
+
+; GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+; GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+; TIMSK
+.equ    TOIE0   =0
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+; TIFR
+.equ    TOV0    =0
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+; SPMCR
+.equ	ASB		=6
+.equ	ASRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+
+.equ    TWIE    =0
+
+; MCUCR
+.equ    SE      =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+; MCUSR
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+; TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+; SFIOR
+.equ    ACME    =3
+.equ    PUD     =2
+.equ    PSR2    =1
+.equ    PSR10   =0
+
+; TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+; TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+; TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+; ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+; WDTCR
+.equ	WDTOE	=4
+.equ	WDE	    =3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+; EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+; PORTA
+.equ	PA7		=7
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+; DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+; PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+; PORTB
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+; DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+; PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+; PORTC
+.equ	PC7		=7
+.equ	PC6		=6
+.equ	PC5		=5
+.equ	PC4		=4
+.equ	PC3		=3
+.equ	PC2		=2
+.equ	PC1		=1
+.equ	PC0		=0
+
+; DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+; PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+; PORTD
+.equ	PD7		=7
+.equ	PD6		=6
+.equ	PD5		=5
+.equ	PD4		=4
+.equ	PD3		=3
+.equ	PD2		=2
+.equ	PD1		=1
+.equ	PD0		=0
+
+; DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+; PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+; SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+; SPCR
+.equ	SPIE	=7
+.equ	SPE	    =6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+; UCSRA
+.equ	RXC	    =7
+.equ	TXC	    =6
+.equ	UDRE	=5
+.equ	FE	    =4
+.equ	OR	    =3
+.equ	U2X	    =1
+.equ	MPCM	=0
+
+; UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+; ACSR
+.equ	ACD	    =7
+.equ    ACBG    =6
+.equ	ACO	    =5
+.equ	ACI	    =4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+; ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+; ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWAR
+.equ    TWGCE   =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	FLASHEND	=$1FFF
+.equ 	E2END	    =$1FF
+.equ	RAMEND	    =$45F
+
+.equ 	BOOTSTART	=$1E00  ;OBSOLETE!!! temporarily kept for compatibility
+;.equ 	LARGEBOOTSTART	=$0C00  ;largest boot block is 2KB
+;.equ 	SMALLBOOTSTART	=$0F80  ;smallest boot block is 256B
+.equ 	SMALLBOOTSTART	=0b1111110000000  ;($1F80) smallest boot block is 256B
+.equ 	SECONDBOOTSTART	=0b1111100000000  ;($1F00) second boot block size is 512B
+.equ 	THIRDBOOTSTART	=0b1111000000000  ;($1E00) third boot block size is 1KB
+.equ 	LARGEBOOTSTART	=0b1110000000000  ;($1C00) largest boot block is 2KB
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+.equ	INT0addr=$002	;External Interrupt0 Vector Address
+.equ	INT1addr=$004	;External Interrupt1 Vector Address
+.equ	OC2addr =$006	;Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$008	;Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$00A	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$00C	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$00E	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$010	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$012	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$014	;SPI Interrupt Vector Address
+.equ	URXCaddr=$016	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$018	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$01A	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$01C	;ADC Interrupt Vector Address
+.equ	ERDYaddr=$01E	;EEPROM Interrupt Vector Address
+.equ	ACIaddr =$020	;Analog Comparator Interrupt Vector Address
+.equ    TWSIaddr=$022   ;Irq. vector address for Two-Wire Interface
diff --git a/include/m169def.inc b/include/m169def.inc
new file mode 100644
index 0000000..c219da9
--- /dev/null
+++ b/include/m169def.inc
@@ -0,0 +1,824 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number			: AVR000
+;* File Name			: "m169def.inc"
+;* Title			: Register/Bit Definitions for the ATmega169
+;* Date                 	: June 14th, 2001
+;* Version              	: 2.0
+;* Support telephone		: +47 72 88 43 88 (ATMEL Norway)
+;* Support fax			: +47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		: support@atmel.no
+;* Target MCU			: ATmega169
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;**** Specify Device ****
+.device ATmega169
+
+;*****************************************************************************
+; I/O Register Definitions
+;*****************************************************************************
+
+;**** Memory Mapped I/O Register Definitions  ****
+.equ  LCDDR18 	= $FE
+.equ  LCDDR17 	= $FD 
+.equ  LCDDR16 	= $FC
+.equ  LCDDR15 	= $FB
+.equ  LCDDR13 	= $F9 
+.equ  LCDDR12 	= $F8
+.equ  LCDDR11 	= $F7
+.equ  LCDDR10 	= $F6 
+.equ  LCDDR8 	= $F4
+.equ  LCDDR7 	= $F3
+.equ  LCDDR6 	= $F2
+.equ  LCDDR5 	= $F1 
+.equ  LCDDR3 	= $EF
+.equ  LCDDR2 	= $EE
+.equ  LCDDR1 	= $ED 
+.equ  LCDDR0 	= $EC
+.equ  LCDCCR 	= $E7
+.equ  LCDFRR 	= $E6
+.equ  LCDCRB 	= $E5
+.equ  LCDCRA 	= $E4
+.equ  UDR0 	= $C6  
+.equ  UBRR0H 	= $C5  
+.equ  UBRR0L 	= $C4  
+.equ  UCSR0C 	= $C2
+.equ  UCSR0B 	= $C1
+.equ  UCSR0A 	= $C0
+.equ  USIDR	= $BA
+.equ  USISR	= $B9
+.equ  USICR	= $B8
+.equ  ASSR 	= $B6
+.equ  OCR2A	= $B3  
+.equ  TCNT2 	= $B2  
+.equ  TCCR2A 	= $B0
+.equ  OCR1BH 	= $8B 
+.equ  OCR1BL 	= $8A 
+.equ  OCR1AH 	= $89 
+.equ  OCR1AL 	= $88 
+.equ  ICR1H 	= $87 
+.equ  ICR1L 	= $86 
+.equ  TCNT1H 	= $85 
+.equ  TCNT1L 	= $84 
+.equ  TCCR1C 	= $82 
+.equ  TCCR1B 	= $81
+.equ  TCCR1A 	= $80
+.equ  DIDR1 	= $7F
+.equ  DIDR0 	= $7E
+.equ  ADMUX 	= $7C 
+.equ  ADCSRB 	= $7B
+.equ  ADCSRA 	= $7A
+.equ  ADCH 	= $79 
+.equ  ADCL 	= $78
+.equ  TIMSK2 	= $70
+.equ  TIMSK1 	= $6F
+.equ  TIMSK0 	= $6E
+.equ  PCMSK1 	= $6C
+.equ  PCMSK0 	= $6B 
+.equ  EICRA 	= $69 
+.equ  OSCCAL 	= $66
+.equ  CLKPR 	= $61
+.equ  WDTCR 	= $60
+.equ  SREG 	= $3F
+.equ  SPH 	= $3E
+.equ  SPL 	= $3D
+.equ  SPMCSR 	= $37
+.equ  MCUCR 	= $35
+.equ  MCUSR 	= $34
+.equ  SMCR 	= $33
+.equ  OCDR 	= $31
+.equ  ACSR 	= $30
+.equ  SPDR 	= $2E 
+.equ  SPSR 	= $2D
+.equ  SPCR 	= $2C
+.equ  GPIOR2 	= $2B 
+.equ  GPIOR1 	= $2A 
+.equ  OCR0A	= $27
+.equ  TCNT0 	= $26 
+.equ  TCCR0A 	= $24
+.equ  GTCCR 	= $23
+.equ  EEARH 	= $22 
+.equ  EEARL 	= $21 
+.equ  EEDR 	= $20
+.equ  EECR 	= $1F
+.equ  GPIOR0 	= $1E 
+.equ  EIMSK 	= $1D
+.equ  EIFR 	= $1C
+.equ  TIFR2 	= $17
+.equ  TIFR1 	= $16
+.equ  TIFR0 	= $15
+.equ  PORTG 	= $14
+.equ  DDRG 	= $13
+.equ  PING 	= $12
+.equ  PORTF 	= $11
+.equ  DDRF 	= $10
+.equ  PINF 	= $0F
+.equ  PORTE 	= $0E
+.equ  DDRE 	= $0D
+.equ  PINE 	= $0C
+.equ  PORTD 	= $0B
+.equ  DDRD 	= $0A
+.equ  PIND 	= $09
+.equ  PORTC 	= $08
+.equ  DDRC 	= $07
+.equ  PINC 	= $06
+.equ  PORTB 	= $05
+.equ  DDRB 	= $04
+.equ  PINB 	= $03
+.equ  PORTA 	= $02
+.equ  DDRA 	= $01
+.equ  PINA 	= $00
+
+;*****************************************************************************
+; Bit Definitions
+;*****************************************************************************
+
+; *** LCDDR18, LCDDR13, LCDDR8, LCDDR3 ***
+.equ SEG24		= 0	
+
+; *** LCDSR17, LCDSR12, LCDSR7, LCDSR2 ***
+.equ SEG23      = 7 
+.equ SEG22      = 6
+.equ SEG21      = 5
+.equ SEG20      = 4
+.equ SEG19      = 3
+.equ SEG18      = 2
+.equ SEG17      = 1
+.equ SEG16      = 0
+
+; *** LCDSR16, LCDSR11, LCDSR6, LCDSR1 ***
+.equ SEG15      = 7 
+.equ SEG14      = 6
+.equ SEG13      = 5
+.equ SEG12      = 4
+.equ SEG11      = 3
+.equ SEG10      = 2
+.equ SEG9       = 1
+.equ SEG8       = 0
+	
+; *** LCDSR15, LCDSR10, LCDSR5, LCDSR0 ***
+.equ SEG7       = 7 
+.equ SEG6       = 6
+.equ SEG5       = 5
+.equ SEG4       = 4
+.equ SEG3       = 3
+.equ SEG2       = 2
+.equ SEG1       = 1
+.equ SEG0       = 0
+
+; *** LCDCCR ***
+.equ LCDCC3     = 3 
+.equ LCDCC2     = 2
+.equ LCDCC1     = 1
+.equ LCDCC0     = 0
+
+; *** LCDFRR *** 
+.equ LCDPS2     = 6 
+.equ LCDPS1     = 5
+.equ LCDPS0     = 4
+.equ LCDCD2     = 2
+.equ LCDCD1     = 1
+.equ LCDCD0     = 0
+				
+; *** LCDCRB ***
+.equ LCDCS      = 7 
+.equ LCDB2	= 6
+.equ LCDMUX1    = 5 
+.equ LCDMUX0    = 4
+.equ LCDPM2     = 2
+.equ LCDPM1     = 1
+.equ LCDPM0     = 0
+		
+; *** LCDCRA ***
+.equ LCDEN      = 7 
+.equ LCDAB      = 6		
+.equ LCDIF      = 4
+.equ LCDIE      = 3
+.equ LCDBL      = 0
+
+; *** UCSR0C ***
+.equ UMSEL0     = 6  
+.equ UPM01      = 5
+.equ UPM00      = 4
+.equ USBS0      = 3
+.equ UCSZ01     = 2
+.equ UCSZ00     = 1
+.equ UCPOL0     = 0
+
+; *** UCSR0B ***
+.equ RXCIE0     = 7  
+.equ TXCIE0     = 6
+.equ UDRIE0     = 5
+.equ RXEN0      = 4
+.equ TXEN0      = 3
+.equ UCSZ02     = 2
+.equ RXB80      = 1
+.equ TXB80      = 0
+
+; *** UCSR0A ***
+.equ RXC0       = 7  
+.equ TXC0       = 6
+.equ UDRE0      = 5
+.equ FE0        = 4
+.equ DOR0       = 3
+.equ PE0        = 2
+.equ U2X0       = 1
+.equ MPCM0      = 0
+
+;*** USISR ***
+.equ USISIF     = 7  
+.equ USIOIF     = 6
+.equ USIPF	= 5
+.equ USIDC	= 4
+.equ USICNT3	= 3
+.equ USICNT2	= 2
+.equ USICNT1	= 1
+.equ USICNT0	= 0
+
+; *** USICR ***
+.equ USISIE     = 7  
+.equ USIOIE     = 6
+.equ USIWM1	= 5
+.equ USIWM0	= 4
+.equ USICS1	= 3
+.equ USICS0	= 2
+.equ USICLK	= 1
+.equ USITC	= 0
+	
+; *** ASSR ***
+.equ EXCLK      = 4
+.equ AS2        = 3  
+.equ TCN2UB     = 2
+.equ OCR2UB     = 1
+.equ TCR2UB     = 0
+
+; *** TCCR2A ***
+.equ FOC2       = 7  
+.equ WGM20      = 6
+.equ COM2A1     = 5
+.equ COM2A0     = 4
+.equ WGM21      = 3
+.equ CS22       = 2
+.equ CS21       = 1
+.equ CS20       = 0
+
+; *** TCCR1C ***
+.equ FOC1A      = 7  
+.equ FOC1B      = 6
+
+; *** TCCR1B ***
+.equ ICNC1      = 7  
+.equ ICES1      = 6
+.equ WGM13      = 4
+.equ WGM12      = 3
+.equ CS12       = 2
+.equ CS11       = 1
+.equ CS10       = 0
+
+; *** TCCR1A ***
+.equ COM1A1     = 7  
+.equ COM1A0     = 6
+.equ COM1B1     = 5
+.equ COM1B0     = 4
+.equ COM1C1     = 3
+.equ COM1C0     = 2
+.equ WGM11      = 1
+.equ WGM10      = 0
+
+; *** DIDR1 ***
+.equ ADC7D      = 7  
+.equ ADC6D      = 6
+.equ ADC5D      = 5
+.equ ADC4D      = 4
+.equ ADC3D      = 3
+.equ ADC2D      = 2
+.equ ADC1D      = 1
+.equ ADC0D      = 0
+
+; *** DIDR0 ***
+.equ AIN1D      = 1  
+.equ AIN0D      = 0
+
+; *** ADMUX ***
+.equ REFS1      = 7  
+.equ REFS0      = 6
+.equ ADLAR      = 5
+.equ MUX4       = 4
+.equ MUX3       = 3
+.equ MUX2       = 2
+.equ MUX1       = 1
+.equ MUX0       = 0
+
+; *** ADCSRB ***
+.equ ADHSM      = 7  
+.equ ACME       = 6
+.equ ADTS2      = 2
+.equ ADTS1      = 1
+.equ ADTS0      = 0
+
+; *** ADCSRA ***
+.equ ADEN       = 7  
+.equ ADSC       = 6
+.equ ADRF       = 5
+.equ ADIF       = 4
+.equ ADIE       = 3
+.equ ADPS2      = 2
+.equ ADPS1      = 1
+.equ ADPS0      = 0
+
+; *** TIMSK2 ***
+.equ OCIE2A     = 1
+.equ TOIE2      = 0
+
+; *** TIMSK1 ***
+.equ ICIE1      = 5  
+.equ OCIE1B     = 2
+.equ OCIE1A     = 1
+.equ TOIE1      = 0
+
+; *** TIMSK0 ***
+.equ OCIE0A     = 1
+.equ TOIE0      = 0
+
+; *** PCMSK1 ***
+.equ PCINT15    = 7  
+.equ PCINT14    = 6
+.equ PCINT13    = 5
+.equ PCINT12    = 4
+.equ PCINT11    = 3
+.equ PCINT10    = 2
+.equ PCINT9     = 1
+.equ PCINT8     = 0
+
+; *** PCMSK0 ***
+.equ PCINT7     = 7  
+.equ PCINT6     = 6
+.equ PCINT5     = 5
+.equ PCINT4     = 4
+.equ PCINT3     = 3
+.equ PCINT2     = 2
+.equ PCINT1     = 1
+.equ PCINT0     = 0
+
+; *** EICRA ***
+.equ ISC01	= 1
+.equ ISC00	= 0
+
+; *** CLKPR ***
+.equ CLKPCE     = 7  
+.equ CLKPS3     = 3
+.equ CLKPS2     = 2
+.equ CLKPS1     = 1
+.equ CLKPS0     = 0
+
+; *** WDTCR ***
+.equ WDCE       = 4  
+.equ WDE        = 3
+.equ WDP2       = 2
+.equ WDP1       = 1
+.equ WDP0       = 0
+
+; *** SREG ***
+.equ I          = 7  
+.equ T          = 6
+.equ H          = 5
+.equ S          = 4
+.equ V          = 3
+.equ N          = 2
+.equ Z          = 1
+.equ C          = 0
+
+; *** SPH ***
+.equ SP15       = 7  
+.equ SP14       = 6
+.equ SP13       = 5
+.equ SP12       = 4
+.equ SP11       = 3
+.equ SP10       = 2
+.equ SP9        = 1
+.equ SP8        = 0
+
+; *** SPL ***
+.equ SP7        = 7  
+.equ SP6        = 6
+.equ SP5        = 5
+.equ SP4        = 4
+.equ SP3        = 3
+.equ SP2        = 2
+.equ SP1        = 1
+.equ SP0        = 0
+
+; *** SPMCSR ***
+.equ SPMIE      = 7  
+.equ RWWSB      = 6
+.equ RWWSRE     = 4
+.equ BLBSET     = 3
+.equ PGWRT      = 2
+.equ PGERS      = 1
+.equ SPMEN      = 0
+
+; *** MCUCR ***
+.equ JTD        = 7  
+.equ PUD        = 4
+.equ IVSEL      = 1
+.equ IVCE       = 0
+
+; *** MCUSR ***
+.equ JTRF       = 4  
+.equ WDRF       = 3
+.equ BORF       = 2
+.equ EXTRF      = 1
+.equ PORF       = 0
+
+; *** SMCR ***
+.equ SM2        = 3  
+.equ SM1        = 2
+.equ SM0        = 1
+.equ SE         = 0
+
+; *** OCDR ***
+.equ IDRD       = 7  
+.equ OCD	= 7
+.equ OCDR6      = 6
+.equ OCDR5      = 5
+.equ OCDR4      = 4
+.equ OCDR3      = 3
+.equ OCDR2      = 2
+.equ OCDR1      = 1
+.equ OCDR0      = 0
+
+; *** ACSR ***
+.equ ACD        = 7  
+.equ ACBG       = 6
+.equ ACO        = 5
+.equ ACI        = 4
+.equ ACIE       = 3
+.equ ACIC       = 2
+.equ ACIS1      = 1
+.equ ACIS0      = 0
+
+; *** SPSR ***
+.equ SPIF       = 7  
+.equ WCOL       = 6
+.equ SPI2X      = 0
+
+; *** SPCR ***
+.equ SPIE       = 7 
+.equ SPE        = 6
+.equ DORD       = 5
+.equ MSTR       = 4
+.equ CPOL       = 3
+.equ CPHA       = 2
+.equ SPR1       = 1
+.equ SPR0       = 0
+
+; *** TCCR0A ***
+.equ FOC0A      = 7 
+.equ WGM00      = 6
+.equ COM0A1     = 5
+.equ COM0A0     = 4
+.equ WGM01      = 3
+.equ CS02       = 2
+.equ CS01       = 1
+.equ CS00       = 0
+
+; *** GTCCR ***
+.equ TSM        = 7  
+.equ PSR2       = 1
+.equ PSR10      = 0
+					 
+; To make tim8pwm_def.inc file
+; part independent.		
+.equ PSR0       = PSR10	 
+.equ PSR1       = PSR10
+	
+; *** EECR ***
+.equ EERIE      = 3  
+.equ EEMWE      = 2
+.equ EEWE       = 1
+.equ EERE       = 0
+
+; *** EIMSK ***
+.equ PCIE1      = 7
+.equ PCIE0      = 6
+.equ INT0       = 0
+
+; *** EIFR ***
+.equ PCIF1      = 7
+.equ PCIF0      = 6
+.equ INTF0      = 0
+
+; *** TIFR2 ***
+.equ OCF2A      = 1
+.equ TOV2       = 0
+
+; *** TIFR1 ***
+.equ ICF1       = 5  
+.equ OCF1B      = 2
+.equ OCF1A      = 1
+.equ TOV1       = 0
+
+; *** TIFR0 ***
+.equ OCF0A      = 1
+.equ TOV0       = 0
+
+; *** PORTG ***
+.equ PORTG5     = 5
+.equ PORTG4     = 4
+.equ PORTG3     = 3
+.equ PORTG2     = 2
+.equ PORTG1     = 1
+.equ PORTG0     = 0
+
+; *** DDRG ***
+.equ DDG4       = 4
+.equ DDG3       = 3
+.equ DDG2       = 2
+.equ DDG1       = 1
+.equ DDG0       = 0
+
+; *** PING ***
+.equ PING5      = 5
+.equ PING4      = 4
+.equ PING3      = 3
+.equ PING2      = 2
+.equ PING1      = 1
+.equ PING0      = 0
+
+; *** PORTF ***
+.equ PORTF7     = 7  
+.equ PORTF6     = 6
+.equ PORTF5     = 5
+.equ PORTF4     = 4
+.equ PORTF3     = 3
+.equ PORTF2     = 2
+.equ PORTF1     = 1
+.equ PORTF0     = 0
+
+; *** DDRF ***
+.equ DDF7       = 7  
+.equ DDF6       = 6
+.equ DDF5       = 5
+.equ DDF4       = 4
+.equ DDF3       = 3
+.equ DDF2       = 2
+.equ DDF1       = 1
+.equ DDF0       = 0
+
+; *** PINF ***
+.equ PINF7      = 7  
+.equ PINF6      = 6
+.equ PINF5      = 5
+.equ PINF4      = 4
+.equ PINF3      = 3
+.equ PINF2      = 2
+.equ PINF1      = 1
+.equ PINF0      = 0
+
+; *** PORTE ***
+.equ PORTE7     = 7  
+.equ PORTE6     = 6
+.equ PORTE5     = 5
+.equ PORTE4     = 4
+.equ PORTE3     = 3
+.equ PORTE2     = 2
+.equ PORTE1     = 1
+.equ PORTE0     = 0
+
+; *** DDRE ***
+.equ DDE7       = 7  
+.equ DDE6       = 6
+.equ DDE5       = 5
+.equ DDE4       = 4
+.equ DDE3       = 3
+.equ DDE2       = 2
+.equ DDE1       = 1
+.equ DDE0       = 0
+
+; *** PINE ***
+.equ PINE7      = 7  
+.equ PINE6      = 6
+.equ PINE5      = 5
+.equ PINE4      = 4
+.equ PINE3      = 3
+.equ PINE2      = 2
+.equ PINE1      = 1
+.equ PINE0      = 0
+
+; *** PORTD ***
+.equ PORTD7     = 7  
+.equ PORTD6     = 6
+.equ PORTD5     = 5
+.equ PORTD4     = 4
+.equ PORTD3     = 3
+.equ PORTD2     = 2
+.equ PORTD1     = 1
+.equ PORTD0     = 0
+
+; *** DDRD ***
+.equ DDD7       = 7  
+.equ DDD6       = 6
+.equ DDD5       = 5
+.equ DDD4       = 4
+.equ DDD3       = 3
+.equ DDD2       = 2
+.equ DDD1       = 1
+.equ DDD0       = 0
+
+; *** PIND ***
+.equ PIND7      = 7  
+.equ PIND6      = 6
+.equ PIND5      = 5
+.equ PIND4      = 4
+.equ PIND3      = 3
+.equ PIND2      = 2
+.equ PIND1      = 1
+.equ PIND0      = 0
+
+; *** PORTC ***
+.equ PORTC7     = 7  
+.equ PORTC6     = 6
+.equ PORTC5     = 5
+.equ PORTC4     = 4
+.equ PORTC3     = 3
+.equ PORTC2     = 2
+.equ PORTC1     = 1
+.equ PORTC0     = 0
+
+; *** DDRC ***
+.equ DDC7       = 7  
+.equ DDC6       = 6
+.equ DDC5       = 5
+.equ DDC4       = 4
+.equ DDC3       = 3
+.equ DDC2       = 2
+.equ DDC1       = 1
+.equ DDC0       = 0
+
+; *** PINC ***
+.equ PINC7      = 7  
+.equ PINC6      = 6
+.equ PINC5      = 5
+.equ PINC4      = 4
+.equ PINC3      = 3
+.equ PINC2      = 2
+.equ PINC1      = 1
+.equ PINC0      = 0
+
+; *** PORTB ***
+.equ PORTB7     = 7  
+.equ PORTB6     = 6
+.equ PORTB5     = 5
+.equ PORTB4     = 4
+.equ PORTB3     = 3
+.equ PORTB2     = 2
+.equ PORTB1     = 1
+.equ PORTB0     = 0
+
+; *** DDRB ***
+.equ DDB7       = 7  
+.equ DDB6       = 6
+.equ DDB5       = 5
+.equ DDB4       = 4
+.equ DDB3       = 3
+.equ DDB2       = 2
+.equ DDB1       = 1
+.equ DDB0       = 0
+
+; *** PINB ***
+.equ PINB7      = 7  
+.equ PINB6      = 6
+.equ PINB5      = 5
+.equ PINB4      = 4
+.equ PINB3      = 3
+.equ PINB2      = 2
+.equ PINB1      = 1
+.equ PINB0      = 0
+
+; *** PORTA ***
+.equ PORTA7     = 7  
+.equ PORTA6     = 6
+.equ PORTA5     = 5
+.equ PORTA4     = 4
+.equ PORTA3     = 3
+.equ PORTA2     = 2
+.equ PORTA1     = 1
+.equ PORTA0     = 0
+
+; *** DDRA ***
+.equ DDA7       = 7  
+.equ DDA6       = 6
+.equ DDA5       = 5
+.equ DDA4       = 4
+.equ DDA3       = 3
+.equ DDA2       = 2
+.equ DDA1       = 1
+.equ DDA0       = 0
+
+; *** PINA ***
+.equ PINA7      = 7  
+.equ PINA6      = 6
+.equ PINA5      = 5
+.equ PINA4      = 4
+.equ PINA3      = 3
+.equ PINA2      = 2
+.equ PINA1      = 1
+.equ PINA0      = 0
+
+;*****************************************************************************
+; CPU Register Declarations
+;*****************************************************************************
+
+.def	XL	= r26		; X pointer low
+.def	XH	= r27		; X pointer high
+.def	YL	= r28		; Y pointer low
+.def	YH	= r29		; Y pointer high
+.def	ZL	= r30		; Z pointer low
+.def	ZH	= r31		; Z pointer high
+
+
+;*****************************************************************************
+; Data Memory Declarations
+;*****************************************************************************
+
+.equ 	RAMEND	= $4ff		; Highest internal data memory (SRAM) address.
+							;(1k RAM + IO + REG)
+.equ	EEPROMEND = $01ff   ; Highest EEPROM address.
+	                        ;(512 byte)
+;*****************************************************************************
+; Program Memory Declarations
+;*****************************************************************************
+
+.equ    FLASHEND = $1FFF	;  Highest program memory (flash) address
+	                        ; (When addressed as 16 bit words)
+							; ( 8k words , 16k byte ) 
+		
+;**** Boot Vectors ****
+			;  byte groups
+			;   /--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b1111110000000  ;($1F80) smallest boot block is 256B
+.equ 	SECONDBOOTSTART	=0b1111100000000  ;($1F00) second boot block size is 512B
+.equ 	THIRDBOOTSTART	=0b1111000000000  ;($1E00) third boot block size is 1KB
+.equ 	LARGEBOOTSTART	=0b1110000000000  ;($1C00) largest boot block is 2KB
+.equ 	BOOTSTART	=THIRDBOOTSTART   ;OBSOLETE!!! kept for compatibility
+
+;**** Page Size ****
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+;**** Interrupt Vectors ****		
+.equ	INT0addr     =$002	;External Interrupt0 Interrupt Address
+.equ	PCINT0addr   =$004	;Pin Change Interrupt0 Interrupt Address 
+.equ	PCINT1addr   =$006	;Pin Change Interrupt1 Interrupt Address
+.equ	CMP2addr     =$008 
+.equ	OC2addr      =$008	;Timer/Counter2 Compare Match Interrupt Address
+.equ	OVF2addr     =$00a	;Overflow1 Interrupt Address
+.equ	ICP1addr     =$00c	;Input Capture1 Interrupt Address
+.equ	OC1Aaddr     =$00e	;Output Compare1A Interrupt Address
+.equ	OC1Baddr     =$010	;Output Compare1B Interrupt Address 
+.equ	OVF1addr     =$012	;Overflow1 Interrupt Address
+.equ	CMP0addr     =$014 
+.equ	OC0addr      =$014	;Timer/Counter0 Compare Match Interrupt Address
+.equ	OVF0addr     =$016	;Overflow0 Interrupt Address
+.equ	SPIaddr      =$018	;SPI Interrupt Address
+.equ	URXC0addr    =$01a	;UART Receive Complete Interrupt Address
+.equ	UDRE0addr    =$01c	;UART Data Register Empty Interrupt Address
+.equ	UTXC0addr    =$01e	;UART Transmit Complete Interrupt Address
+.equ	USI_STARTaddr=$020	;Universal Serial Bus Start Interrupt Address   
+.equ	USI_OVFaddr  =$022	;Universal Serial Bus Overflow Interrupt Address	
+.equ	ACIaddr	     =$024	;Analog Comparator Interrupt Address
+.equ  ADCCaddr     =$026	;ADC Conversion Complete Interrupt Address
+.equ	ERDYaddr     =$028	;EEPROM write complete Interrupt Address
+.equ	SPMRaddr     =$02a	;Store Program Memory Ready Interrupt Address
+.equ	LCDSFaddr    =$02c	;LCD Start of Frame Interrupt Address
+
+;for compatibility with s8515
+.equ	URXCaddr=$01a	;UART Receive Complete Interrupt 
+.equ	UDREaddr=$01e	;UART Data Register Empty Interrupt 
+.equ	UTXCaddr=$022	;UART Transmit Complete Interrupt 
+
diff --git a/include/m16def.inc b/include/m16def.inc
new file mode 100644
index 0000000..3a08f89
--- /dev/null
+++ b/include/m16def.inc
@@ -0,0 +1,508 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"m16def.inc"
+;* Title				:Register/Bit Definitions for the ATmega16
+;* Date                 :07.09.2001
+;* Version              :1.00
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax			:+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.no
+;* Target MCU			:ATmega16
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega16
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	OCR0	=$3c		
+.equ	GICR	=$3b		; New name for GIMSK
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    I2CR    =$36
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ    MCUCSR	=$34		; New name for MCUSR
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRHI  =$20
+.equ    UBRRH   =$20		; New name for UBRRHI
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	UCSRA	=$0b
+.equ	USR		=$0b    ; For compatibility with S8535
+.equ	UCSRB	=$0a
+.equ	UCR		=$0a    ; For compatibility with S8535
+.equ	UCSRC	=$20	; Note! UCSRC equals UBRRH 
+.equ	UBRR	=$09
+.equ	UBRRL	=$09	; New name for UBRR
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+.equ    I2DR    =$03
+.equ    I2AR    =$02
+.equ    I2SR    =$01
+.equ    I2BR    =$00
+
+;***** Bit Definitions
+
+; GIMSK / GICR
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5	
+.equ	IVSEL	=1      
+.equ	IVCE	=0      
+	
+; GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5       
+
+; TIMSK
+.equ    TOIE0   =0
+.equ    OCIE0   =1	 
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+; TIFR
+.equ    TOV0    =0
+.equ    OCF0    =1	 
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+; SPMCR
+.equ	SPMIE	=7
+.equ	ASB	=6
+.equ	ASRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+	
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+
+.equ    TWIE    =0
+
+; MCUCR
+	
+.equ    SM2     =7   
+.equ    SE      =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+; MCUSR
+.equ    ISC2    =6   
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+; TCCR0
+.equ    FOC0    =7   
+.equ    PWM0    =6  ;OBSOLETE! Use WGM00
+.equ    WGM00   =6
+.equ	COM01	=5   
+.equ	COM00	=4   
+.equ	CTC0	=3  ;OBSOLETE! Use WGM01
+.equ    WGM01   =3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+; SFIOR
+.equ	ADTS2	=7	 			
+.equ	ADTS1	=6	 			
+.equ	ADTS0	=5	 			
+.equ    ADHSM   =4
+.equ    ACME    =3
+.equ    PUD     =2
+.equ    PSR2    =1
+.equ    PSR10   =0
+
+; TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1  ; OBSOLETE! Use WGM11
+.equ	PWM10	=0  ; OBSOLETE! Use WGM10
+.equ	WGM11	=1
+.equ	WGM10	=0
+
+; TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC11	=4  ; OBSOLETE! Use WGM13
+.equ	CTC10	=3  ; OBSOLETE! Use WGM12
+.equ	CTC1	=3  ; OBSOLETE! Use WGM12
+.equ	WGM13	=4
+.equ	WGM12	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+; TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6  ; OBSOLETE! Use WGM20
+.equ    WGM20   =6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3  ; OBSOLETE! Use WGM21
+.equ    WGM21   =3
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+; ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+; WDTCR
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+; EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+; PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+; DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+; PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+; PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+; DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+; PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+; PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+; DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+; PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+; PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+; DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+; PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+; SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+; SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+; UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3
+.equ	DOR	=3	;New name for OR
+.equ	PE	=2	 
+.equ	U2X	=1
+.equ	MPCM	=0
+
+; UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	UCSZ2	=2	; New name for CHR9
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7	 
+.equ	UMSEL	=6	 
+.equ	UPM1	=5	 
+.equ	UPM0	=4	 
+.equ	USBS	=3	 
+.equ	UCSZ1	=2	 
+.equ	UCSZ0	=1	 
+.equ	UCPOL	=0	 
+
+; ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+; ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+; ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ	ADATE	=5	 
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWAR
+.equ    TWGCE   =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND =$45F
+
+.equ 	BOOTSTART	=$1E00  ;OBSOLETE!!! temporarily kept for compatibility
+;.equ 	LARGEBOOTSTART	=$0C00  ;largest boot block is 2KB
+;.equ 	SMALLBOOTSTART	=$0F80  ;smallest boot block is 256B
+.equ 	SMALLBOOTSTART	=0b1111110000000  ;($1F80) smallest boot block is 256B
+.equ 	SECONDBOOTSTART	=0b1111100000000  ;($1F00) second boot block size is 512B
+.equ 	THIRDBOOTSTART	=0b1111000000000  ;($1E00) third boot block size is 1KB
+.equ 	LARGEBOOTSTART	=0b1110000000000  ;($1C00) largest boot block is 2KB
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+.equ 	FLASHEND	=$1fff
+
+.equ	INT0addr=$002	;External Interrupt0 Vector Address
+.equ	INT1addr=$004	;External Interrupt1 Vector Address
+.equ	OC2addr =$006	;Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$008	;Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$00A	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$00C	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$00E	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$010	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$012	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$014	;SPI Interrupt Vector Address
+.equ	URXCaddr=$016	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$018	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$01A	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$01C	;ADC Interrupt Vector Address
+.equ	ERDYaddr=$01E	;EEPROM Interrupt Vector Address
+.equ	ACIaddr =$020	;Analog Comparator Interrupt Vector Address
+.equ    TWIaddr =$022   ;Irq. vector address for Two-Wire Interface
+.equ	INT2addr=$024   ;External Interrupt2 Vector Address
+.equ	OC0addr =$026   ;Output Compare0 Interrupt Vector Address
+.equ	SPMRaddr=$028   ;Store Program Memory Ready Interrupt Vector Address
diff --git a/include/m323def.inc b/include/m323def.inc
new file mode 100644
index 0000000..60b923a
--- /dev/null
+++ b/include/m323def.inc
@@ -0,0 +1,498 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		        :AVR000
+;* File Name		    :"m323def.inc"
+;* Title		        :Register/Bit Definitions for the ATmega323
+;* Date                 :99.08.25
+;* Version              :1.00
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		    :+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	    :avr@atmel.no
+;* Target MCU		    :ATmega323
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega323
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH	    =$3e
+.equ	SPL	    =$3d
+.equ	OCR0	=$3c
+.equ	GIMSK	=$3b		; For compatibility, keep both names until further
+.equ	GICR	=$3b		; new name for GIMSK
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34		; For compatibility, 
+.equ    MCUCSR  =$34		; keep both names until further
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRH   =$20		;  Note! UCSRC equals UBRRH
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	    =$0c
+.equ	UCSRA	=$0b
+.equ	UCSRB	=$0a
+.equ	UCSRC	=$20		;  Note! UCSRC equals UBRRH
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+
+
+;***** Bit Definitions
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+.equ	IVSEL	=1		; interrupt vector select
+.equ	IVCE	=0		; interrupt vector change enable
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+
+;TIMSK
+.equ    TOIE0   =0
+.equ    OCIE0   =1
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+;TIFR
+.equ    TOV0    =0
+.equ    OCF0    =1
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	ASB	=6
+.equ	ASRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;MCUCR
+.equ    SE      =7
+.equ    SM2     =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+;MCUCSR
+.equ	JTD     =7	
+.equ    ISC2    =6
+.equ    EIH     =5
+.equ    JTRF    =4	
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+;TCCR0
+.equ    FOC0    =7
+.equ    PWM0    =6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	CTC0	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC11	=4
+.equ	CTC10	=3
+.equ	CTC1	=3		; Obsolete - Included for backward compatibility
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+;SFIOR
+.equ    RPDD    =7
+.equ    RPDC    =6
+.equ    RPDB    =5
+.equ    RPDA    =4
+.equ    ACME    =3
+.equ    PUD     =2
+.equ	PSR2	=1
+.equ	PSR10	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3		; old name kept for compatibilty
+.equ	DOR	=3
+.equ	PE	=2
+.equ	U2X	=1
+.equ	MPCM	=0
+
+;UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7
+.equ	UMSEL	=6
+.equ	UPM1	=5
+.equ	UPM0	=4
+.equ	USBS	=3
+.equ	UCSZ1	=2
+.equ	UCSZ0	=1
+.equ	UCPOL	=0
+		
+;SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+.equ    TWI_TST =1  ;Present in core test mode only. Write Only.
+.equ    TWIE    =0
+
+; TWAR
+.equ    TWGCE   =0
+
+;ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	FLASHEND	=$3FFF
+.equ 	E2END	    =$3FF
+.equ	RAMEND	    =$85F
+
+			;  byte groups
+			;  /\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b11111100000000  ;($3F00) smallest boot block is 256W
+.equ 	SECONDBOOTSTART	=0b11111000000000  ;($3E00) 2'nd boot block size is 512W
+.equ 	THIRDBOOTSTART	=0b11110000000000  ;($3C00) third boot block size is 1KW
+.equ 	LARGEBOOTSTART	=0b11100000000000  ;($3800) largest boot block is 2KW
+.equ 	BOOTSTART	=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+
+.equ	INT0addr=$002	; External Interrupt0 Vector Address
+.equ	INT1addr=$004	; External Interrupt1 Vector Address
+.equ	INT2addr=$006	; External Interrupt2 Vector Address
+.equ	OC2addr =$008	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$00a	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$00c	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$00e	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$010	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$012	; Overflow1 Interrupt Vector Address
+.equ	OC0addr =$014	; Output Compare0 Interrupt Vector Address
+.equ	OVF0addr=$016	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$018	; SPI Interrupt Vector Address
+.equ	URXCaddr=$01a	; USART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$01c	; USART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$01e	; USART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$020	; ADC Interrupt Vector Address
+.equ	ERDYaddr=$022	; EEPROM Interrupt Vector Address
+.equ	ACIaddr =$024	; Analog Comparator Interrupt Vector Address
+.equ    TWSIaddr=$026   ; Irq. vector address for Two-Wire Interface
+.equ	SPMRaddr=$028	; Store Program Memory Ready Interrupt Vector Address
+
+
+
diff --git a/include/m32def.inc b/include/m32def.inc
new file mode 100644
index 0000000..2603975
--- /dev/null
+++ b/include/m32def.inc
@@ -0,0 +1,498 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		        :AVR000
+;* File Name		    :"m32def.inc"
+;* Title		        :Register/Bit Definitions for the ATmega32
+;* Date                 :99.08.25
+;* Version              :1.00
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		    :+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	    :avr@atmel.no
+;* Target MCU		    :ATmega32
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega32
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH	    =$3e
+.equ	SPL	    =$3d
+.equ	OCR0	=$3c
+.equ	GIMSK	=$3b		; For compatibility, keep both names until further
+.equ	GICR	=$3b		; new name for GIMSK
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34		; For compatibility, 
+.equ    MCUCSR  =$34		; keep both names until further
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRH   =$20		;  Note! UCSRC equals UBRRH
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	    =$0c
+.equ	UCSRA	=$0b
+.equ	UCSRB	=$0a
+.equ	UCSRC	=$20		;  Note! UCSRC equals UBRRH
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+
+
+;***** Bit Definitions
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+.equ	IVSEL	=1		; interrupt vector select
+.equ	IVCE	=0		; interrupt vector change enable
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+
+;TIMSK
+.equ    TOIE0   =0
+.equ    OCIE0   =1
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+;TIFR
+.equ    TOV0    =0
+.equ    OCF0    =1
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	ASB	=6
+.equ	ASRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;MCUCR
+.equ    SE      =7
+.equ    SM2     =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+;MCUCSR
+.equ	JTD     =7	
+.equ    ISC2    =6
+.equ    EIH     =5
+.equ    JTRF    =4	
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+;TCCR0
+.equ    FOC0    =7
+.equ    PWM0    =6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	CTC0	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC11	=4
+.equ	CTC10	=3
+.equ	CTC1	=3		; Obsolete - Included for backward compatibility
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+;SFIOR
+.equ    RPDD    =7
+.equ    RPDC    =6
+.equ    RPDB    =5
+.equ    RPDA    =4
+.equ    ACME    =3
+.equ    PUD     =2
+.equ	PSR2	=1
+.equ	PSR10	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3		; old name kept for compatibilty
+.equ	DOR	=3
+.equ	PE	=2
+.equ	U2X	=1
+.equ	MPCM	=0
+
+;UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7
+.equ	UMSEL	=6
+.equ	UPM1	=5
+.equ	UPM0	=4
+.equ	USBS	=3
+.equ	UCSZ1	=2
+.equ	UCSZ0	=1
+.equ	UCPOL	=0
+		
+;SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+.equ    TWI_TST =1  ;Present in core test mode only. Write Only.
+.equ    TWIE    =0
+
+; TWAR
+.equ    TWGCE   =0
+
+;ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	FLASHEND	=$3FFF
+.equ 	E2END	    =$3FF
+.equ	RAMEND	    =$85F
+
+			;  byte groups
+			;  /\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b11111100000000  ;($3F00) smallest boot block is 256W
+.equ 	SECONDBOOTSTART	=0b11111000000000  ;($3E00) 2'nd boot block size is 512W
+.equ 	THIRDBOOTSTART	=0b11110000000000  ;($3C00) third boot block size is 1KW
+.equ 	LARGEBOOTSTART	=0b11100000000000  ;($3800) largest boot block is 2KW
+.equ 	BOOTSTART	=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+
+.equ	INT0addr=$002	; External Interrupt0 Vector Address
+.equ	INT1addr=$004	; External Interrupt1 Vector Address
+.equ	INT2addr=$006	; External Interrupt2 Vector Address
+.equ	OC2addr =$008	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$00a	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$00c	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$00e	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$010	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$012	; Overflow1 Interrupt Vector Address
+.equ	OC0addr =$014	; Output Compare0 Interrupt Vector Address
+.equ	OVF0addr=$016	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$018	; SPI Interrupt Vector Address
+.equ	URXCaddr=$01a	; USART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$01c	; USART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$01e	; USART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$020	; ADC Interrupt Vector Address
+.equ	ERDYaddr=$022	; EEPROM Interrupt Vector Address
+.equ	ACIaddr =$024	; Analog Comparator Interrupt Vector Address
+.equ    TWSIaddr=$026   ; Irq. vector address for Two-Wire Interface
+.equ	SPMRaddr=$028	; Store Program Memory Ready Interrupt Vector Address
+
+
+
diff --git a/include/m64def.inc b/include/m64def.inc
new file mode 100644
index 0000000..a4a7f06
--- /dev/null
+++ b/include/m64def.inc
@@ -0,0 +1,954 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				: AVR000
+;* File Name			: "m64def.inc"
+;* Title				: Register/Bit Definitions for the ATmega604
+;* Date                 : April 16th, 2002
+;* Version              : 1.0
+;* Support telephone	: +47 72 88 43 88 (ATMEL Norway)
+;* Support fax			: +47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		: support@atmel.no
+;* Target MCU			: ATmega64
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;**** Specify Device ****
+.device ATmega64
+
+;*****************************************************************************
+; I/O Register Definitions
+;*****************************************************************************
+
+;**** Memory Mapped I/O Register Definitions ($FF-$60) ****
+.equ	UCSR1C	= $9D
+.equ	UDR1	= $9C
+.equ	UCSR1A	= $9B
+.equ	UCSR1B	= $9A
+.equ	UBRR1L	= $99
+.equ	UBRR1H	= $98
+.equ	UCSR0C	= $95
+.equ	UBRR0H	= $90
+.equ	ADCSRB  = $8E
+.equ	TCCR3C	= $8C
+.equ	TCCR3A	= $8B
+.equ	TCCR3B	= $8A
+.equ	TCNT3H	= $89
+.equ	TCNT3L	= $88
+.equ	OCR3AH	= $87
+.equ	OCR3AL	= $86
+.equ	OCR3BH	= $85
+.equ	OCR3BL	= $84
+.equ	OCR3CH	= $83
+.equ	OCR3CL	= $82
+.equ	ICR3H	= $81
+.equ	ICR3L	= $80
+.equ	ETIMSK	= $7D
+.equ	ETIFR	= $7C
+.equ	TCCR1C	= $7A
+.equ	OCR1CH	= $79
+.equ	OCR1CL	= $78
+.equ	I2CR	= $74
+.equ	I2DR	= $73
+.equ	I2AR	= $72
+.equ	I2SR	= $71
+.equ	I2BR	= $70
+.equ	TWCR	= $74
+.equ	TWDR	= $73
+.equ	TWAR	= $72
+.equ	TWSR	= $71
+.equ	TWBR	= $70
+.equ	OSCCAL	= $6F
+.equ	XMCRA	= $6D
+.equ	XMCRB	= $6C
+.equ	EICRA	= $6A
+.equ	SPMCSR	= $68
+.equ	SPMCR	= $68		; old name for SPMCSR
+.equ	PORTG	= $65
+.equ	DDRG	= $64
+.equ	PING	= $63
+.equ	PORTF	= $62
+.equ	DDRF	= $61
+
+;**** I/O Register Definitions ($3F-$00) ****
+.equ	SREG	= $3F
+.equ	SPH		= $3E
+.equ	SPL		= $3D
+.equ	XDIV	= $3C
+.equ	EICRB	= $3A
+.equ	EIMSK	= $39
+.equ	GIMSK	= $39		; old name for EIMSK
+.equ	GICR	= $39		; old name for EIMSK
+.equ	EIFR	= $38
+.equ	GIFR	= $38		; old name for EIFR
+.equ	TIMSK	= $37
+.equ	TIFR	= $36
+.equ	MCUCR	= $35
+.equ	MCUCSR	= $34
+.equ	TCCR0	= $33
+.equ	TCNT0	= $32
+.equ	OCR0	= $31
+.equ	ASSR	= $30
+.equ	TCCR1A	= $2F
+.equ	TCCR1B	= $2E
+.equ	TCNT1H	= $2D
+.equ	TCNT1L	= $2C
+.equ	OCR1AH	= $2B
+.equ	OCR1AL	= $2A
+.equ	OCR1BH	= $29
+.equ	OCR1BL	= $28
+.equ	ICR1H	= $27
+.equ	ICR1L	= $26
+.equ	TCCR2	= $25
+.equ	TCNT2	= $24
+.equ	OCR2	= $23
+.equ	OCDR	= $22		; New
+.equ	WDTCR	= $21
+.equ	SFIOR	= $20		; New
+.equ	EEARH	= $1F
+.equ	EEARL	= $1E
+.equ	EEDR	= $1D
+.equ	EECR	= $1C
+.equ	PORTA	= $1B
+.equ	DDRA	= $1A
+.equ	PINA	= $19
+.equ	PORTB	= $18
+.equ	DDRB	= $17
+.equ	PINB	= $16
+.equ	PORTC	= $15
+.equ	DDRC	= $14		; New
+.equ	PINC	= $13		; New
+.equ	PORTD	= $12
+.equ	DDRD	= $11
+.equ	PIND	= $10
+.equ	SPDR	= $0F
+.equ	SPSR	= $0E
+.equ	SPCR	= $0D
+.equ	UDR0	= $0C
+.equ	UCSR0A	= $0B
+.equ	UCSR0B	= $0A
+.equ	UBRR0L	= $09
+.equ	ACSR	= $08
+.equ	ADMUX	= $07
+.equ	ADCSRA	= $06	
+.equ	ADCSR	= $06
+.equ	ADCH	= $05
+.equ	ADCL	= $04
+.equ	PORTE	= $03
+.equ	DDRE	= $02
+.equ	PINE	= $01
+.equ	PINF	= $00
+
+
+;*****************************************************************************
+; Bit Definitions
+;*****************************************************************************
+
+; **** MCU Control ****
+; **** MCUCR ****
+.equ	SRE		= 7		
+.equ	SRW10	= 6
+.equ	SE		= 5
+.equ	SM1		= 4
+.equ	SM0		= 3
+.equ	SM2		= 2
+.equ	IVSEL	= 1
+.equ	IVCE	= 0
+
+; **** MCUCSR ****
+.equ	JTD		= 7		
+.equ	JTRF	= 4	
+.equ	WDRF	= 3
+.equ	BORF	= 2
+.equ	EXTRF	= 1
+.equ	PORF	= 0
+
+; **** XMCRA ****
+.equ	SRL2	= 6		
+.equ	SRL1	= 5
+.equ	SRL0	= 4
+.equ	SRW01	= 3
+.equ	SRW00	= 2
+.equ	SRW11	= 1
+
+; **** XMCRB ****
+.equ	XMBK	= 7		
+.equ	XMM2	= 2
+.equ	XMM1	= 1
+.equ	XMM0	= 0
+
+; **** SPMCSR ****
+.equ	SPMIE	= 7		
+.equ	ASB		= 6		; backwards compatiblity
+.equ	ASRE	= 4		; backwards compatiblity
+.equ	RWWSB	= 6
+.equ	RWWSRE	= 4	
+.equ	BLBSET	= 3
+.equ	PGWRT	= 2
+.equ	PGERS	= 1
+.equ	SPMEN	= 0
+
+; **** OCDR ****
+.equ	IDRD	= 7		
+.equ	OCDR6	= 6
+.equ	OCDR5	= 5
+.equ	OCDR4	= 4	
+.equ	OCDR3	= 3
+.equ	OCDR2	= 2
+.equ	OCDR1	= 1
+.equ	OCDR0	= 0
+
+; **** XDIV ****
+.equ	XDIVEN	= 7		
+.equ	XDIV6	= 6
+.equ	XDIV5	= 5
+.equ	XDIV4	= 4
+.equ	XDIV3	= 3
+.equ	XDIV2	= 2
+.equ	XDIV1	= 1
+.equ	XDIV0	= 0
+
+; **** SFIOR ****
+.equ	TSM		= 7		
+.equ	ADHSM	= 4
+.equ	ACME	= 3
+.equ	PUD		= 2
+.equ	PSR0	= 1
+.equ	PSR1	= 0
+.equ	PSR2	= 0
+.equ	PSR3	= 0
+.equ	PSR321	= 0	
+
+; **** Analog to Digital Converter ****
+; **** ADCSR ****
+.equ	ADEN	= 7		
+.equ	ADSC	= 6
+.equ	ADATE	= 5
+.equ	ADFR	= 5
+.equ	ADIF	= 4
+.equ	ADIE	= 3
+.equ	ADPS2	= 2
+.equ	ADPS1	= 1
+.equ	ADPS0	= 0
+
+; **** ADMUX ****
+.equ    REFS1   = 7		
+.equ    REFS0   = 6
+.equ    ADLAR   = 5
+.equ    MUX4    = 4
+.equ    MUX3    = 3
+.equ    MUX2    = 2
+.equ    MUX1    = 1
+.equ    MUX0    = 0
+
+; **** ADCSRB ****
+.equ	ADTS2	= 2		
+.equ	ADTS1	= 1
+.equ	ADTS0	= 0	
+
+;**** Analog Comparator ****
+; **** ACSR ****
+.equ	ACD		= 7		
+.equ	ACBG	= 6
+.equ	ACO		= 5
+.equ	ACI		= 4
+.equ	ACIE	= 3
+.equ	ACIC	= 2
+.equ	ACIS1	= 1
+.equ	ACIS0	= 0
+	
+
+; **** External Interrupts ****
+; **** EIMSK ****
+.equ	INT7	= 7		
+.equ	INT6	= 6
+.equ	INT5	= 5
+.equ	INT4	= 4
+.equ	INT3	= 3
+.equ	INT2	= 2
+.equ	INT1	= 1
+.equ	INT0	= 0
+
+; **** EIFR ****
+.equ	INTF7	= 7		
+.equ	INTF6	= 6
+.equ	INTF5	= 5
+.equ	INTF4	= 4
+.equ	INTF3	= 3
+.equ	INTF2	= 2
+.equ	INTF1	= 1
+.equ	INTF0	= 0
+
+; **** EICRB ****
+.equ	ISC71	= 7		
+.equ	ISC70	= 6
+.equ	ISC61	= 5
+.equ	ISC60	= 4
+.equ	ISC51	= 3
+.equ	ISC50	= 2
+.equ	ISC41	= 1
+.equ	ISC40	= 0
+
+; **** EICRA ****
+.equ	ISC31	= 7		
+.equ	ISC30	= 6
+.equ	ISC21	= 5
+.equ	ISC20	= 4
+.equ	ISC11	= 3
+.equ	ISC10	= 2
+.equ	ISC01	= 1
+.equ	ISC00	= 0
+
+; **** Timer Interrupts ****
+; **** TIMSK ****
+.equ	OCIE2	= 7		
+.equ	TOIE2	= 6
+.equ	TICIE1	= 5
+.equ	OCIE1A	= 4
+.equ	OCIE1B	= 3
+.equ	TOIE1	= 2
+.equ	OCIE0	= 1
+.equ	TOIE0	= 0
+
+; **** ETIMSK ****
+.equ	TICIE3	= 5		
+.equ	OCIE3A	= 4
+.equ	OCIE3B	= 3
+.equ	TOIE3	= 2
+.equ	OCIE3C	= 1
+.equ	OCIE1C	= 0
+
+; **** TIFR ****
+.equ	OCF2	= 7		
+.equ	TOV2	= 6
+.equ	ICF1	= 5
+.equ	OCF1A	= 4
+.equ	OCF1B	= 3
+.equ	TOV1	= 2
+.equ	OCF0	= 1
+.equ	TOV0	= 0
+
+; **** ETIFR ****
+.equ	ICF3	= 5		
+.equ	OCF3A	= 4
+.equ	OCF3B	= 3
+.equ	TOV3	= 2
+.equ	OCF3C	= 1
+.equ	OCF1C	= 0
+
+; **** Asynchronous Timer ****
+; **** ASSR ****
+.equ	AS0		= 3		
+.equ	TCN0UB	= 2
+.equ	OCR0UB	= 1
+.equ	TCR0UB	= 0
+
+; **** Timer 0 ****
+; **** TCCR0 ****
+.equ    FOC0    = 7		
+.equ    PWM0    = 6
+.equ    WGM00   = 6	
+.equ	COM01	= 5
+.equ	COM00	= 4
+.equ	CTC0	= 3
+.equ    WGM01   = 3
+.equ	CS02	= 2
+.equ	CS01	= 1
+.equ	CS00	= 0
+
+; **** Timer 1 ****
+; **** TCCR1A ****
+.equ	COM1A1	= 7		
+.equ	COM1A0	= 6
+.equ	COM1B1	= 5
+.equ	COM1B0	= 4
+.equ	COM1C1	= 3
+.equ	COM1C0	= 2
+.equ	PWM11	= 1		; OBSOLETE! Use WGM11
+.equ	PWM10	= 0		; OBSOLETE! Use WGM10
+.equ	WGM11	= 1
+.equ	WGM10	= 0
+
+; **** TCCR1B ****
+.equ	ICNC1	= 7		
+.equ	ICES1	= 6
+.equ	CTC11	= 4		; OBSOLETE! Use WGM13
+.equ	CTC10	= 3		; OBSOLETE! Use WGM12
+.equ	WGM13	= 4
+.equ	WGM12	= 3
+.equ	CS12	= 2
+.equ	CS11	= 1
+.equ	CS10	= 0
+
+; **** TCCR1C ****
+.equ	FOC1A	= 7		
+.equ	FOC1B	= 6
+.equ	FOC1C	= 5
+
+; **** Timer 2 ****
+; **** TCCR2 ****
+.equ	FOC2	= 7		
+.equ	PWM2	= 6
+.equ    WGM20   = 6	
+.equ	COM21	= 5
+.equ	COM20	= 4
+.equ	CTC2	= 3
+.equ    WGM21   = 3
+.equ	CS22	= 2
+.equ	CS21	= 1
+.equ	CS20	= 0
+
+; **** Timer 3 ****
+; **** TCCR3A ****
+.equ	COM3A1	= 7		
+.equ	COM3A0	= 6
+.equ	COM3B1	= 5
+.equ	COM3B0	= 4
+.equ	COM3C1	= 3
+.equ	COM3C0	= 2
+.equ	PWM31	= 1		; OBSOLETE! Use WGM31
+.equ	PWM30	= 0		; OBSOLETE! Use WGM30
+.equ	WGM31	= 1
+.equ	WGM30	= 0
+
+; **** TCCR3B ****  
+.equ	ICNC3	= 7		
+.equ	ICES3	= 6
+.equ	CTC31	= 4		; OBSOLETE! Use WGM33
+.equ	CTC30	= 3		; OBSOLETE! Use WGM32
+.equ	WGM33	= 4
+.equ	WGM32	= 3
+.equ	CS32	= 2
+.equ	CS31	= 1
+.equ	CS30	= 0
+
+; **** TCCR3C ****
+.equ	FOC3A	= 7		
+.equ	FOC3B	= 6
+.equ	FOC3C	= 5
+
+; **** Watchdog Timer ****
+; **** WDTCR ****
+.equ	WDCE	= 4		
+.equ	WDTOE	= 4		; For Mega103 compability
+.equ	WDE		= 3
+.equ	WDP2	= 2
+.equ	WDP1	= 1
+.equ	WDP0	= 0
+
+; **** EEPROM  Control Register ****
+; **** EECR ****
+.equ	EERIE	= 3		
+.equ	EEMWE	= 2
+.equ	EEWE	= 1
+.equ	EERE	= 0
+
+; **** USART 0 and USART 1 ****
+; **** (UCSRA0/1) ****
+.equ	RXC		= 7		
+.equ	TXC		= 6
+.equ	UDRE	= 5
+.equ	FE		= 4
+.equ	DOR		= 3
+.equ	PE		= 2		; OBSOLETED!
+.equ	U2X		= 1
+.equ	MPCM	= 0
+
+; **** (UCSR0A) ****
+.equ	RXC0	= 7		
+.equ	TXC0	= 6
+.equ	UDRE0	= 5
+.equ	FE0		= 4
+.equ	DOR0	= 3
+.equ	UPE0	= 2
+.equ	U2X0	= 1
+.equ	MPCM0	= 0
+
+; **** (UCSR1A) ****
+.equ	RXC1	= 7		
+.equ	TXC1	= 6
+.equ	UDRE1	= 5
+.equ	FE1		= 4
+.equ	DOR1	= 3
+.equ	UPE1	= 2
+.equ	U2X1	= 1
+.equ	MPCM1	= 0
+
+; **** (UCSRB0/1) ****
+.equ	RXCIE	= 7		
+.equ	TXCIE	= 6
+.equ	UDRIE	= 5
+.equ	RXEN	= 4
+.equ	TXEN	= 3
+.equ	UCSZ2	= 2
+.equ	RXB8	= 1
+.equ	TXB8	= 0
+
+; **** (UCSR0B) ****
+.equ	RXCIE0	= 7		
+.equ	TXCIE0	= 6
+.equ	UDRIE0	= 5
+.equ	RXEN0	= 4
+.equ	TXEN0	= 3
+.equ	UCSZ02	= 2
+.equ	RXB80	= 1
+.equ	TXB80	= 0
+
+; **** (UCSR1B) ****
+.equ	RXCIE1	= 7		
+.equ	TXCIE1	= 6
+.equ	UDRIE1	= 5
+.equ	RXEN1	= 4
+.equ	TXEN1	= 3
+.equ	UCSZ12	= 2
+.equ	RXB81	= 1
+.equ	TXB81	= 0
+
+; **** (UCSRC0/1) ****
+.equ	UMSEL	= 6		
+.equ	UPM1	= 5
+.equ	UPM0	= 4
+.equ	USBS	= 3
+.equ	UCSZ1	= 2
+.equ	UCSZ0	= 1
+.equ	UCPOL	= 0
+
+; **** (UCSR0C) ****
+.equ	UMSEL0	= 6		
+.equ	UPM01	= 5
+.equ	UPM00	= 4
+.equ	USBS0	= 3
+.equ	UCSZ01	= 2
+.equ	UCSZ00	= 1
+.equ	UCPOL0	= 0
+
+; **** (UCSR1C) ****
+.equ	UMSEL1	= 6		
+.equ	UPM11	= 5
+.equ	UPM10	= 4
+.equ	USBS1	= 3
+.equ	UCSZ11	= 2
+.equ	UCSZ10	= 1
+.equ	UCPOL1	= 0
+
+	
+; **** SPI ****
+; **** SPCR ****
+.equ	SPIE	= 7		
+.equ	SPE		= 6
+.equ	DORD	= 5
+.equ	MSTR	= 4
+.equ	CPOL	= 3
+.equ	CPHA	= 2
+.equ	SPR1	= 1
+.equ	SPR0	= 0
+
+; **** SPSR ****
+.equ	SPIF	= 7		
+.equ	WCOL	= 6
+.equ	SPI2X	= 0
+
+; **** I2C/TWI ****
+; **** I2CR ****
+.equ	I2INT	= 7		
+.equ	I2EA	= 6
+.equ	I2STA	= 5
+.equ	I2STO	= 4
+.equ	I2WC	= 3
+.equ	ENI2C	= 2
+.equ    I2EN    = 2
+.equ	I2C_TST	= 1		; Present in core test mode only. Write Only.
+.equ	I2IE	= 0
+
+; **** I2SR ****
+.equ	I2S7	= 7		
+.equ	I2S6	= 6
+.equ	I2S5	= 5
+.equ	I2S4	= 4
+.equ	I2S3	= 3
+.equ	I2GCE	= 0		
+	
+; **** I2AR ****
+.equ	TWINT	= 7
+.equ	TWEA	= 6
+.equ	TWSTA	= 5
+.equ	TWSTO	= 4
+.equ	TWWC	= 3
+.equ    TWEN    = 2
+.equ	TWC_TST	= 1		; Present in core test mode only. Write Only.
+.equ	TWIE	= 0
+
+; **** TWSR ****
+.equ	TWS7	= 7		
+.equ	TWS6	= 6
+.equ	TWS5	= 5
+.equ	TWS4	= 4
+.equ	TWS3	= 3
+.equ	TWPS1	= 1
+.equ	TWPS0	= 0
+
+; **** TWAR ****
+.equ	TWA6	= 7
+.equ	TWA5	= 6
+.equ	TWA4	= 5
+.equ	TWA3	= 4
+.equ	TWA2	= 3
+.equ	TWA1	= 2
+.equ	TWA0	= 1
+.equ	TWGCE	= 0
+
+; **** PORT A ****
+; **** PORTA ****
+.equ	PA7		= 7		
+.equ	PA6		= 6
+.equ	PA5		= 5
+.equ	PA4		= 4
+.equ	PA3		= 3
+.equ	PA2		= 2
+.equ	PA1		= 1
+.equ	PA0		= 0
+.equ	PORTA7	= 7
+.equ	PORTA6	= 6
+.equ	PORTA5	= 5
+.equ	PORTA4	= 4
+.equ	PORTA3	= 3
+.equ	PORTA2	= 2
+.equ	PORTA1	= 1
+.equ	PORTA0	= 0
+
+; **** DDRA ****
+.equ	DDA7	= 7		
+.equ	DDA6	= 6
+.equ	DDA5	= 5
+.equ	DDA4	= 4
+.equ	DDA3	= 3
+.equ	DDA2	= 2
+.equ	DDA1	= 1
+.equ	DDA0	= 0
+
+; **** PINA ****
+.equ	PINA7	= 7		
+.equ	PINA6	= 6
+.equ	PINA5	= 5
+.equ	PINA4	= 4
+.equ	PINA3	= 3
+.equ	PINA2	= 2
+.equ	PINA1	= 1
+.equ	PINA0	= 0
+
+; **** PORT B ****
+; **** PORTB ****
+.equ	PB7		= 7		
+.equ	PB6		= 6
+.equ	PB5		= 5
+.equ	PB4		= 4
+.equ	PB3		= 3
+.equ	PB2		= 2
+.equ	PB1		= 1
+.equ	PB0		= 0
+.equ	PORTB7	= 7
+.equ	PORTB6	= 6
+.equ	PORTB5	= 5
+.equ	PORTB4	= 4
+.equ	PORTB3	= 3
+.equ	PORTB2	= 2
+.equ	PORTB1	= 1
+.equ	PORTB0	= 0
+
+; **** DDRB ****
+.equ	DDB7	= 7		
+.equ	DDB6	= 6
+.equ	DDB5	= 5
+.equ	DDB4	= 4
+.equ	DDB3	= 3
+.equ	DDB2	= 2
+.equ	DDB1	= 1
+.equ	DDB0	= 0
+
+; **** PINB ****
+.equ	PINB7	= 7		
+.equ	PINB6	= 6
+.equ	PINB5	= 5
+.equ	PINB4	= 4
+.equ	PINB3	= 3
+.equ	PINB2	= 2
+.equ	PINB1	= 1
+.equ	PINB0	= 0
+
+;**** PORTC ****
+.equ	PC7		= 7		
+.equ	PC6		= 6
+.equ	PC5		= 5
+.equ	PC4		= 4
+.equ	PC3		= 3
+.equ	PC2		= 2
+.equ	PC1		= 1
+.equ	PC0		= 0
+.equ	PORTC7	= 7
+.equ	PORTC6	= 6
+.equ	PORTC5	= 5
+.equ	PORTC4	= 4
+.equ	PORTC3	= 3
+.equ	PORTC2	= 2
+.equ	PORTC1	= 1
+.equ	PORTC0	= 0
+
+; **** DDRC ****
+.equ	DDC7	= 7		
+.equ	DDC6	= 6
+.equ	DDC5	= 5
+.equ	DDC4	= 4
+.equ	DDC3	= 3
+.equ	DDC2	= 2
+.equ	DDC1	= 1
+.equ	DDC0	= 0
+
+; **** PINC ****
+.equ	PINC7	= 7		
+.equ	PINC6	= 6
+.equ	PINC5	= 5
+.equ	PINC4	= 4
+.equ	PINC3	= 3
+.equ	PINC2	= 2
+.equ	PINC1	= 1
+.equ	PINC0	= 0
+
+;**** PORTD ****
+.equ	PD7		= 7	
+.equ	PD6		= 6
+.equ	PD5		= 5
+.equ	PD4		= 4
+.equ	PD3		= 3
+.equ	PD2		= 2
+.equ	PD1		= 1
+.equ	PD0		= 0
+.equ	PORTD7	= 7
+.equ	PORTD6	= 6
+.equ	PORTD5	= 5
+.equ	PORTD4	= 4
+.equ	PORTD3	= 3
+.equ	PORTD2	= 2
+.equ	PORTD1	= 1
+.equ	PORTD0	= 0
+
+; **** DDRD ****
+.equ	DDD7	= 7		
+.equ	DDD6	= 6
+.equ	DDD5	= 5
+.equ	DDD4	= 4
+.equ	DDD3	= 3
+.equ	DDD2	= 2
+.equ	DDD1	= 1
+.equ	DDD0	= 0
+
+; **** PIND ****
+.equ	PIND7	= 7		
+.equ	PIND6	= 6
+.equ	PIND5	= 5
+.equ	PIND4	= 4
+.equ	PIND3	= 3
+.equ	PIND2	= 2
+.equ	PIND1	= 1
+.equ	PIND0	= 0
+
+;**** PORTE ****
+.equ	PE7		= 7
+.equ	PE6		= 6
+.equ	PE5		= 5
+.equ	PE4		= 4
+.equ	PE3		= 3
+.equ	PE2		= 2
+.equ	PE1		= 1
+.equ	PE0		= 0
+.equ	PORTE7	= 7
+.equ	PORTE6	= 6
+.equ	PORTE5	= 5
+.equ	PORTE4	= 4
+.equ	PORTE3	= 3
+.equ	PORTE2	= 2
+.equ	PORTE1	= 1
+.equ	PORTE0	= 0
+
+; **** DDRE ****
+.equ	DDE7	= 7		
+.equ	DDE6	= 6
+.equ	DDE5	= 5
+.equ	DDE4	= 4
+.equ	DDE3	= 3
+.equ	DDE2	= 2
+.equ	DDE1	= 1
+.equ	DDE0	= 0
+
+; **** PINE ****
+.equ	PINE7	= 7		
+.equ	PINE6	= 6
+.equ	PINE5	= 5
+.equ	PINE4	= 4
+.equ	PINE3	= 3
+.equ	PINE2	= 2
+.equ	PINE1	= 1
+.equ	PINE0	= 0
+
+; **** PORTF ****
+.equ	PF7		= 7		
+.equ	PF6		= 6
+.equ	PF5		= 5
+.equ	PF4		= 4
+.equ	PF3		= 3
+.equ	PF2		= 2
+.equ	PF1		= 1
+.equ	PF0		= 0
+.equ	PORTF7	= 7
+.equ	PORTF6	= 6
+.equ	PORTF5	= 5
+.equ	PORTF4	= 4
+.equ	PORTF3	= 3
+.equ	PORTF2	= 2
+.equ	PORTF1	= 1
+.equ	PORTF0	= 0
+
+; **** DDRF ****
+.equ	DDF7	= 7		
+.equ	DDF6	= 6
+.equ	DDF5	= 5
+.equ	DDF4	= 4
+.equ	DDF3	= 3
+.equ	DDF2	= 2
+.equ	DDF1	= 1
+.equ	DDF0	= 0
+
+; **** PINF ****
+.equ	PINF7	= 7		
+.equ	PINF6	= 6
+.equ	PINF5	= 5
+.equ	PINF4	= 4
+.equ	PINF3	= 3
+.equ	PINF2	= 2
+.equ	PINF1	= 1
+.equ	PINF0	= 0
+
+; **** PORTG ****
+.equ	PG4		= 4		
+.equ	PG3		= 3
+.equ	PG2		= 2		
+.equ	PG1		= 1
+.equ	PG0		= 0
+
+; **** DDRG ****
+.equ	DDG4	= 4		
+.equ	DDG3	= 3
+.equ	DDG2	= 2
+.equ	DDG1	= 1
+.equ	DDG0	= 0
+
+; **** PING ****
+.equ	PING4	= 4
+.equ	PING3	= 3	
+.equ	PING2	= 2
+.equ	PING1	= 1
+.equ	PING0	= 0
+
+
+;*****************************************************************************
+; CPU Register Declarations
+;*****************************************************************************
+
+.def	XL	= r26		; X pointer low
+.def	XH	= r27		; X pointer high
+.def	YL	= r28		; Y pointer low
+.def	YH	= r29		; Y pointer high
+.def	ZL	= r30		; Z pointer low
+.def	ZH	= r31		; Z pointer high
+
+
+;*****************************************************************************
+; Data Memory Declarations
+;*****************************************************************************
+
+.equ 	RAMEND	= $10ff		; Highest internal data memory (SRAM) address.
+.equ	EEPROMEND = $07ff       ; Highest EEPROM address.
+	
+;*****************************************************************************
+; Program Memory Declarations
+;*****************************************************************************
+
+.equ    FLASHEND = $7FFF	;  Highest program memory (flash) address
+	                        ; (When addressed as 16 bit words)
+		
+;**** Boot Vectors ****
+			 ;  byte groups
+			 ;  /--\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	= 0b0111111000000000	; ($7E00) Smallest boot block is 512W
+.equ 	SECONDBOOTSTART	= 0b0111110000000000	; ($7C00) 2'nd boot block size is 1KW
+.equ 	THIRDBOOTSTART	= 0b0111100000000000	; ($7800) Third boot block size is 2KW
+.equ 	LARGEBOOTSTART	= 0b0111000000000000	; ($7000) Largest boot block is 4KW
+
+
+;**** Page Size ****
+.equ	PAGESIZE	= 128	; Number of WORDS in a page
+
+
+;**** Interrupt Vectors ****
+.equ	INT0addr  = $002	; External Interrupt0 Vector Address
+.equ	INT1addr  = $004	; External Interrupt1 Vector Address
+.equ	INT2addr  = $006	; External Interrupt2 Vector Address
+.equ	INT3addr  = $008	; External Interrupt3 Vector Address
+.equ	INT4addr  = $00a	; External Interrupt4 Vector Address
+.equ	INT5addr  = $00c	; External Interrupt5 Vector Address
+.equ	INT6addr  = $00e	; External Interrupt6 Vector Address
+.equ	INT7addr  = $010	; External Interrupt7 Vector Address
+.equ	OC2addr   = $012	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr  = $014	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr  = $016	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr  = $018	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr  = $01a	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr  = $01c	; Overflow1 Interrupt Vector Address
+.equ	OC0addr   = $01e	; Output Compare0 Interrupt Vector Address
+.equ	OVF0addr  = $020	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr   = $022	; SPI Interrupt Vector Address
+.equ	URXC0addr = $024	; USART0 Receive Complete Interrupt Vector Address
+.equ	UDRE0addr = $026	; USART0 Data Register Empty Interrupt Vector Address
+.equ	UTXC0addr = $028	; USART0 Transmit Complete Interrupt Vector Address
+.equ    ADCCaddr  = $02a	; ADC Conversion Complete Handle
+.equ	ERDYaddr  = $02c	; EEPROM Write Complete Handle
+.equ	ACIaddr   = $02e	; Analog Comparator Interrupt Vector Address
+
+.equ	OC1Caddr  = $030	; Output Compare1C Interrupt Vector Address
+.equ	ICP3addr  = $032	; Input Capture3 Interrupt Vector Address
+.equ	OC3Aaddr  = $034	; Output Compare3A Interrupt Vector Address
+.equ	OC3Baddr  = $036	; Output Compare3B Interrupt Vector Address
+.equ	OC3Caddr  = $038	; Output Compare3C Interrupt Vector Address
+.equ	OVF3addr  = $03A	; Overflow3 Interrupt Vector Address
+.equ	URXC1addr = $03C	; USART1 Receive Complete Interrupt Vector Address
+.equ	UDRE1addr = $03E	; USART1 Data Register Empty Interrupt Vector Address
+.equ	UTXC1addr = $040	; USART1 Transmit Complete Interrupt Vector Address
+.equ    I2Caddr   = $042	; I2C Interrupt Vector Address
+.equ    TWIaddr   = $042	; TWI Interrupt Vector Address
+.equ	SPMRaddr  = $044	; Store Program Memory Ready Interrupt Vector Address
+
+
+;**** End of File ****
diff --git a/include/m83def.inc b/include/m83def.inc
new file mode 100644
index 0000000..d43f8f2
--- /dev/null
+++ b/include/m83def.inc
@@ -0,0 +1,465 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		        :AVR000
+;* File Name		    :"m83def.inc"
+;* Title		        :Register/Bit Definitions for the ATmega83
+;* Date                 :00.12.12
+;* Version              :
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax		    :+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail	    :avr@atmel.no
+;* Target MCU		    :ATmega83
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+;.device ATmega83
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH	    =$3e
+.equ	SPL	    =$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRHI  =$20
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	=$0c
+.equ	UCSRA	=$0b
+.equ	USR	=$0b    ; For compatibility with S8535
+.equ	UCSRB	=$0a
+.equ	UCR	=$0a    ; For compatibility with S8535
+.equ	UBRR	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+
+;***** Bit Definitions
+
+; GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+
+; GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+; TIMSK
+.equ    TOIE0   =0
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+; TIFR
+.equ    TOV0    =0
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+; SPMCR
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+.equ    TWI_TST =1  ;Present in core test mode only. Write Only.
+.equ    TWIE    =0
+
+; MCUCR
+.equ    SE      =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+; MCUSR
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+; TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+; SFIOR
+.equ    ACME    =3
+.equ    PUD     =2
+.equ    PSR2    =1
+.equ    PSR10   =0
+
+; TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1
+.equ	PWM10	=0
+
+; TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+; TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+; ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+; WDTCR
+.equ	WDTOE	=4
+.equ	WDE	    =3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+; EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+; PORTA
+.equ	PA7	    =7
+.equ	PA6	    =6
+.equ	PA5	    =5
+.equ	PA4	    =4
+.equ	PA3	    =3
+.equ	PA2	    =2
+.equ	PA1 	=1
+.equ	PA0	    =0
+
+; DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+; PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+; PORTB
+.equ	PB7	    =7
+.equ	PB6	    =6
+.equ	PB5	    =5
+.equ	PB4	    =4
+.equ	PB3	    =3
+.equ	PB2	    =2
+.equ	PB1	    =1
+.equ	PB0	    =0
+
+; DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+; PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+; PORTC
+.equ	PC7	    =7
+.equ	PC6	    =6
+.equ	PC5	    =5
+.equ	PC4	    =4
+.equ	PC3	    =3
+.equ	PC2	    =2
+.equ	PC1	    =1
+.equ	PC0	    =0
+
+; DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+; PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+; PORTD
+.equ	PD7	    =7
+.equ	PD6	    =6
+.equ	PD5	    =5
+.equ	PD4 	=4
+.equ	PD3	    =3
+.equ	PD2	    =2
+.equ	PD1 	=1
+.equ	PD0	    =0
+
+; DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+; PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+; SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+; SPCR
+.equ	SPIE	=7
+.equ	SPE	    =6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+; UCSRA
+.equ	RXC	    =7
+.equ	TXC	    =6
+.equ	UDRE	=5
+.equ	FE	    =4
+.equ	OR	    =3
+.equ	U2X	    =1
+.equ	MPCM	=0
+
+; UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+; ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+; ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+; ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWAR
+.equ    TWA6    =7
+.equ    TWA5    =6
+.equ    TWA4    =5
+.equ    TWA3    =4
+.equ    TWA2    =3
+.equ    TWA1    =2
+.equ    TWA0    =1
+.equ    TWGCE   =0
+
+; TWSR
+.equ    TWS7    =7
+.equ    TWS6    =6
+.equ    TWS5    =5
+.equ    TWS4    =4
+.equ    TWS3    =3
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	FLASHEND	=$1FFF
+.equ 	E2END	    =$1FF
+.equ 	RAMEND      =$25F
+
+.equ 	BOOTSTART	=$1E00  ;OBSOLETE!!! temporarily kept for compatibility
+;.equ 	LARGEBOOTSTART	=$0C00  ;largest boot block is 2KB
+;.equ 	SMALLBOOTSTART	=$0F80  ;smallest boot block is 256B
+.equ 	SMALLBOOTSTART	=0b1111110000000  ;($1F80) smallest boot block is 256B
+.equ 	SECONDBOOTSTART	=0b1111100000000  ;($1F00) second boot block size is 512B
+.equ 	THIRDBOOTSTART	=0b1111000000000  ;($1E00) third boot block size is 1KB
+.equ 	LARGEBOOTSTART	=0b1110000000000  ;($1C00) largest boot block is 2KB
+.equ	PAGESIZE	=64     ;number of WORDS in a page
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	OC2addr =$003	;Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$004	;Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$005	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$006	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$007	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$008	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$009	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$00a	;SPI Interrupt Vector Address
+.equ	URXCaddr=$00b	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00c	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00d	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$00e	;ADC Interrupt Vector Address
+.equ	ERDYaddr=$00f	;EEPROM Interrupt Vector Address
+.equ	ACIaddr =$010	;Analog Comparator Interrupt Vector Address
+.equ    TWSIaddr=$011   ;Irq. vector address for Two-Wire Interface
diff --git a/include/m8515def.inc b/include/m8515def.inc
new file mode 100644
index 0000000..8a4cd41
--- /dev/null
+++ b/include/m8515def.inc
@@ -0,0 +1,464 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"m8515def.inc"
+;* Title				:Register/Bit Definitions for the ATmega8515
+;* Date                 :April 16th, 2002
+;* Version              :1.00
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax			:+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail		:support@atmel.no
+;* Target MCU			:ATmega8515
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega8515
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GICR	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ	EMCUCR	=$36
+.equ	MCUCR	=$35
+.equ    MCUSR   =$34		; For compatibility, 
+.equ    MCUCSR  =$34		; keep both names until further	
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	OCR0	=$31
+.equ	SFIOR   =$30	
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$25
+.equ	ICR1L	=$24
+.equ	WDTCR	=$21
+.equ	UCSRC	=$20		; Note! UCSRC equals UBRRH
+.equ	UBRRH	=$20		; Note! UCSRC equals UBRRH		
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	UCSRA	=$0b
+.equ	UCSRB	=$0a
+.equ	UBRR	=$09		; for AT90S8515
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ	PORTE	=$07
+.equ	DDRE	=$06
+.equ	PINE	=$05
+.equ	OSCCAL	=$04		; New
+
+;***** Bit Definitions
+;GIMSK
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+.equ	IVSEL	=1		; interrupt vector select
+.equ	IVCE	=0		; interrupt vector change enable
+		
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+
+;TIMSK
+.equ	TOIE1	=7
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ	TICIE1	=3
+.equ	TOIE0	=1
+.equ	OCIE0	=0
+
+;TIFR
+.equ	TOV1	=7
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	ICF1	=3
+.equ	TOV0	=1
+.equ	OCF0	=0
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	RWWSB	=6
+.equ	ASB		=6		; old
+.equ	RWWSRE	=4
+.equ	ASRE	=4		; old
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;EMCUCR
+.equ    SM0     =7
+.equ	SRL2	=6
+.equ	SRL1	=5
+.equ	SRL0	=4
+.equ	SRW01	=3
+.equ	SRW00	=2
+.equ	SRW11	=1
+.equ	ISC2	=0
+
+;MCUCR
+.equ	SRE	=7
+.equ	SRW	=6
+.equ	SRW10	=6	
+.equ	SE	=5
+.equ	SM	=4
+.equ	SM1	=4	
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;MCUSR
+.equ	SM2     =5	
+.equ	WDRF	=3
+.equ	BORF	=2
+.equ	EXTRF	=1
+.equ	PORF	=0
+	
+;TCCR0
+.equ    FOC0    =7
+.equ    WGM00   =6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	WGM01	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	= 7
+.equ	COM1A0	= 6
+.equ	COM1B1	= 5
+.equ	COM1B0	= 4
+.equ	FOC1A	= 3
+.equ	FOC1B	= 2
+.equ	PWM11	= 1		; OBSOLETE! Use WGM11
+.equ	PWM10	= 0		; OBSOLETE! Use WGM10
+.equ	WGM11	= 1
+.equ	WGM10	= 0
+
+;TCCR1B
+.equ	ICNC1	= 7
+.equ	ICES1	= 6
+.equ	CTC11	= 4		; OBSOLETE! Use WGM13
+.equ	CTC10	= 3		; OBSOLETE! Use WGM12
+.equ	WGM13	= 4
+.equ	WGM12	= 3
+.equ	CS12	= 2
+.equ	CS11	= 1
+.equ	CS10	= 0
+
+
+;SFIOR
+.equ	TSM	=7
+.equ	XMBK	=6
+.equ	XMM2	=5
+.equ	XMM1	=4
+.equ	XMM0	=3		
+.equ    PUD     =2
+.equ	PSR10	=0
+
+;WDTCR
+.equ	WDTOE	=4
+.equ	WDCE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEWEE	=2
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;PORTE
+.equ	PE2	=2
+.equ	PE1	=1
+.equ	PE0	=0
+
+;DDRE
+.equ	DDE2	=2
+.equ	DDE1	=1
+.equ	DDE0	=0
+
+;PINE
+.equ	PINE2	=2
+.equ	PINE1	=1
+.equ	PINE0	=0
+	
+;UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3		; old name kept for compatibilty
+.equ	DOR	=3
+.equ	PE	=2
+.equ	UPE	=2
+.equ	U2X	=1
+.equ	MPCM	=0
+
+;UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7
+.equ	UMSEL	=6
+.equ	UPM1	=5
+.equ	UPM0	=4
+.equ	USBS	=3
+.equ	UCSZ1	=2
+.equ	UCSZ0	=1
+.equ	UCPOL	=0
+	
+;SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;ACSR
+.equ	ACD	=7
+.equ	AINBG	=6
+.equ	ACBG	=6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND =$25F
+.equ	EEPROMEND = $1FF
+.equ	FLASHEND = $FFF
+	
+			;  byte groups
+			;  /\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b00111110000000  ;($0F80) smallest boot block is 128W
+.equ 	SECONDBOOTSTART	=0b00111100000000  ;($0F00) 2'nd boot block size is 256W
+.equ 	THIRDBOOTSTART	=0b00111000000000  ;($0E00) third boot block size is 512W
+.equ 	LARGEBOOTSTART	=0b00110000000000  ;($0C00) largest boot block is 1KW
+.equ 	BOOTSTART	=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE	=32     ;number of WORDS in a page
+
+	
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	ICP1addr=$003	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$004	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$005	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$006	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$007	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$008	;SPI Interrupt Vector Address
+.equ	URXCaddr=$009	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00a	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00b	;UART Transmit Complete Interrupt Vector Address
+.equ	ACIaddr =$00c	;Analog Comparator Interrupt Vector Address
+
+.equ	INT2addr=$00d	;External Interrupt2 Vector Address
+.equ	OC0addr= $00e	;Output Compare0 Interrupt Vector Address
+.equ	ERDYaddr=$00f	; EEPROM Interrupt Vector Address
+.equ	SPMaddr =$010	; SPM complete Interrupt Vector Address
+.equ	SPMRaddr =$010	; SPM complete Interrupt Vector Address
diff --git a/include/m8535def.inc b/include/m8535def.inc
new file mode 100644
index 0000000..d10493a
--- /dev/null
+++ b/include/m8535def.inc
@@ -0,0 +1,535 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"m8535def.inc"
+;* Title				:Register/Bit Definitions for the ATmega8535
+;* Date                 : April 16th, 2002
+;* Version              :1.00
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:support@atmel.no
+;* Target MCU			:ATmega8535
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega8535
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	OCR0	=$3c
+.equ	GIMSK	=$3b
+.equ	GICR	=$3b			;new name for GIMSK
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    I2CR    =$36
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34			;For compatibility, 
+.equ    MCUCSR  =$34			;keep both names until further
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRH   =$20			;Note! UCSRC equals UBRRH
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTA	=$1b
+.equ	DDRA	=$1a
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR		=$0c
+.equ	UCSRA	=$0b
+.equ	UCSRB	=$0a
+.equ	UCSRC	=$20			;Note! UCSRC equals UBRRH
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSRA  =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    I2DR    =$03
+.equ    I2AR    =$02
+.equ    I2SR    =$01
+.equ    I2BR    =$00
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+;***** Bit definitions*****	  
+;GICR
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	INT2	=5
+.equ	IVSEL	=1		; interrupt vector select
+.equ	IVCE	=0		; interrupt vector change enable
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	INTF2	=5
+
+;TIMSK
+.equ    TOIE0   =0
+.equ    OCIE0   =1
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+;TIFR
+.equ    TOV0    =0
+.equ    OCF0    =1
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	RWWSB	=6
+.equ	RWWSRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;MCUCR
+.equ    SM2     =7
+.equ    SE      =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+;MCUCSR
+.equ    ISC2    =6
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+;TCCR0
+.equ    FOC0    =7
+.equ    PWM0    =6		; OBSOLETE! Use WGM00
+.equ	WGM00	=6
+.equ	COM01	=5
+.equ	COM00	=4
+.equ	CTC0	=3		; OBSOLETE! Use WGM01
+.equ	WGM01	=3	
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1		; OBSOLETE! Use WGM11
+.equ	PWM10	=0		; OBSOLETE! Use WGM10
+.equ	WGM11	=1
+.equ	WGM10	=0
+
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC1	=3		; OBSOLETE! Use WGM12
+.equ	CTC11	=4		; OBSOLETE! Use WGM13
+.equ	CTC10	=3		; OBSOLETE! Use WGM12
+.equ	WGM13	=4
+.equ	WGM12	=3
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6		; OBSOLETE! Use WGM20
+.equ	WGM20	=6
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3		; OBSOLETE! Use WGM21
+.equ	WGM21	=3		
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+;SFIOR
+.equ    ADTS2   =7
+.equ    ADTS1   =6
+.equ    ADTS0   =5
+.equ    ADHSM   =4
+.equ    ACME    =3
+.equ    PUD     =2
+.equ	PSR2	=1
+.equ	PSR10	=0
+
+;WDTCR
+.equ	WDCE	=4
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTA
+.equ	PA7	=7
+.equ	PA6	=6
+.equ	PA5	=5
+.equ	PA4	=4
+.equ	PA3	=3
+.equ	PA2	=2
+.equ	PA1	=1
+.equ	PA0	=0
+
+;DDRA
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;PINA
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC7	=7
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC7	=7
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC7	=7
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3		; old name kept for compatibilty
+.equ	DOR	=3
+.equ	PE	=2		; old name kept for compatibilty
+.equ	UPE	=2
+.equ	U2X	=1
+.equ	MPCM	=0
+
+;UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7
+.equ	UMSEL	=6
+.equ	UPM1	=5
+.equ	UPM0	=4
+.equ	USBS	=3
+.equ	UCSZ1	=2
+.equ	UCSZ0	=1
+.equ	UCPOL	=0
+		
+;SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX4    =4
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSRA
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ	ADATE	=5	
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+;I2CR
+.equ    I2INT   =7
+.equ    I2EA    =6
+.equ    I2STA   =5
+.equ    I2STO   =4
+.equ    I2WC    =3
+.equ    ENI2C   =2
+.equ    I2EN    =2
+.equ    I2C_TST =1  ;Present in core test mode only. Write Only.
+.equ    I2IE    =0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+.equ    TWI_TST =1  ;Present in core test mode only. Write Only.
+.equ    TWIE    =0
+
+;I2AR
+.equ    I2GCE   =0
+
+; TWAR
+.equ	TWA6	=7
+.equ	TWA5	=6
+.equ	TWA4	=5
+.equ	TWA3	=4
+.equ	TWA2	=3
+.equ	TWA1	=2
+.equ	TWA0	=1
+.equ    TWGCE   =0
+
+; TWSR
+.equ	TWS7	=7
+.equ	TWS6	=6
+.equ	TWS5	=5
+.equ	TWS4	=4
+.equ	TWS3	=3
+.equ	TWS2	=2
+.equ	TWS1	=1
+.equ	TWS0	=0
+
+;ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND	=$25F
+			;  byte groups
+			;  /\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b00111110000000  ;($0F80) smallest boot block is 128W
+.equ 	SECONDBOOTSTART	=0b00111100000000  ;($0F00) 2'nd boot block size is 256W
+.equ 	THIRDBOOTSTART	=0b00111000000000  ;($0E00) third boot block size is 512W
+.equ 	LARGEBOOTSTART	=0b00110000000000  ;($0C00) largest boot block is 1KW
+.equ 	BOOTSTART	=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE	=32     ;number of WORDS in a page
+.equ 	FLASHEND	=$fff
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	INT1addr=$002	;External Interrupt1 Vector Address
+.equ	OC2addr	=$003	;Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$004	;Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$005	;Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$006	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$007	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$008	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$009	;Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$00a	;SPI Interrupt Vector Address
+.equ	URXCaddr=$00b	;UART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00c	;UART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00d	;UART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$00e	;ADC Interrupt Vector Address
+.equ	ERDYaddr=$00f	;EEPROM Interrupt Vector Address
+.equ	ACIaddr =$010	;Analog Comparator Interrupt Vector Address
+.equ    TWIaddr =$011   ;Irq. vector address for Two-Wire Interface
+.equ    I2Caddr =$011   ; Irq. vector address for Inter Intergrated Circuit interface
+.equ	INT2addr=$012   ;External Interrupt2 Vector Address
+.equ	OC0addr =$013   ;Output Compare0 Interrupt Vector Address
+.equ	SPMRaddr=$014   ;Store Program Memory Ready Interrupt Vector Address
diff --git a/include/m8def.inc b/include/m8def.inc
new file mode 100644
index 0000000..ab3873b
--- /dev/null
+++ b/include/m8def.inc
@@ -0,0 +1,466 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"m8def.inc"
+;* Title				:Register/Bit Definitions for the ATmega8
+;* Date                 :07.09.2001
+;* Version              :1.00
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax			:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail		:avr@atmel.no
+;* Target MCU			:ATmega8
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATmega8
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPH		=$3e
+.equ	SPL		=$3d
+.equ	GIMSK	=$3b
+.equ	GICR	=$3b		; new name for GIMSK
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	SPMCR	=$37
+.equ    I2CR    =$36
+.equ    TWCR    =$36
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34		; For compatibility, 
+.equ    MCUCSR  =$34		; keep both names until further
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ    OSCCAL  =$31
+.equ    SFIOR   =$30
+.equ	TCCR1A	=$2f
+.equ	TCCR1B	=$2e
+.equ	TCNT1H	=$2d
+.equ	TCNT1L	=$2c
+.equ	OCR1AH	=$2b
+.equ	OCR1AL	=$2a
+.equ	OCR1BH	=$29
+.equ	OCR1BL	=$28
+.equ	ICR1H	=$27
+.equ	ICR1L	=$26
+.equ	TCCR2	=$25
+.equ	TCNT2	=$24
+.equ	OCR2	=$23
+.equ	ASSR	=$22
+.equ	WDTCR	=$21
+.equ    UBRRH   =$20		;  Note! UCSRC equals UBRRH
+.equ	EEARH	=$1f
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	PORTC	=$15
+.equ	DDRC	=$14
+.equ	PINC	=$13
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	SPDR	=$0f
+.equ	SPSR	=$0e
+.equ	SPCR	=$0d
+.equ	UDR	=$0c
+.equ	UCSRA	=$0b
+.equ	UCSRB	=$0a
+.equ	UCSRC	=$20		;  Note! UCSRC equals UBRRH
+.equ	UBRRL	=$09
+.equ	ACSR	=$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+.equ    I2DR    =$03
+.equ    I2AR    =$02
+.equ    I2SR    =$01
+.equ    I2BR    =$00
+.equ    TWDR    =$03
+.equ    TWAR    =$02
+.equ    TWSR    =$01
+.equ    TWBR    =$00
+
+
+
+;***** Bit Definitions
+;GICR  (former GIMSK)
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	IVSEL	=1		; interrupt vector select
+.equ	IVCE	=0		; interrupt vector change enable
+
+;GIFR
+.equ	INTF1	=7
+.equ	INTF0	=6
+
+;TIMSK
+.equ    TOIE0   =0
+.equ    TOIE1   =2
+.equ    OCIE1B  =3
+.equ    OCIE1A  =4
+.equ    TICIE1  =5
+.equ    TOIE2   =6
+.equ    OCIE2   =7
+
+;TIFR
+.equ    TOV0    =0
+.equ    TOV1    =2
+.equ    OCF1B   =3
+.equ    OCF1A   =4
+.equ    ICF1    =5
+.equ    TOV2    =6
+.equ    OCF2    =7
+
+;SPMCR
+.equ	SPMIE	=7
+.equ	RWWSB	=6
+.equ	RWWSRE	=4
+.equ	BLBSET	=3
+.equ	PGWRT	=2
+.equ	PGERS	=1
+.equ	SPMEN	=0
+
+;MCUCR
+.equ    SE      =7
+.equ    SM2     =6
+.equ    SM1     =5
+.equ    SM0     =4
+.equ    ISC11   =3
+.equ    ISC10   =2
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+;MCUCSR
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+;TCCR0
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+;TCCR1A
+.equ	COM1A1	=7
+.equ	COM1A0	=6
+.equ	COM1B1	=5
+.equ	COM1B0	=4
+.equ	FOC1A	=3
+.equ	FOC1B	=2
+.equ	PWM11	=1	; OBSOLETE! Use WGM11
+.equ	PWM10	=0	; OBSOLETE! Use WGM10
+.equ	WGM11	=1
+.equ	WGM10	=0
+;TCCR1B
+.equ	ICNC1	=7
+.equ	ICES1	=6
+.equ	CTC11	=4	; OBSOLETE! Use WGM13
+.equ	CTC10	=3	; OBSOLETE! Use WGM12
+.equ	WGM13	=4
+.equ	WGM12	=3	
+.equ	CTC1	=3		; Obsolete - Included for backward compatibility
+.equ	CS12	=2
+.equ	CS11	=1
+.equ	CS10	=0
+
+;TCCR2
+.equ	FOC2	=7
+.equ    PWM2    =6	; OBSOLETE! Use WGM20
+.equ	WGM20	=6	
+.equ    COM21   =5
+.equ    COM20   =4
+.equ    CTC2    =3	; OBSOLETE! Use WGM21
+.equ	WGM21	=3	
+.equ    CS22    =2
+.equ    CS21    =1
+.equ    CS20    =0
+
+;SFIOR
+.equ    ADHSM   =4
+.equ    ACME    =3
+.equ    PUD     =2
+.equ	PSR2	=1
+.equ	PSR10	=0
+
+;WDTCR
+.equ	WDCE	=4
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;EECR
+.equ    EERIE   =3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;PORTB
+.equ	PB7	=7
+.equ	PB6	=6
+.equ	PB5	=5
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+;DDRB
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;PINB
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;PORTC
+.equ	PC6	=6
+.equ	PC5	=5
+.equ	PC4	=4
+.equ	PC3	=3
+.equ	PC2	=2
+.equ	PC1	=1
+.equ	PC0	=0
+
+;DDRC
+.equ	DDC6	=6
+.equ	DDC5	=5
+.equ	DDC4	=4
+.equ	DDC3	=3
+.equ	DDC2	=2
+.equ	DDC1	=1
+.equ	DDC0	=0
+
+;PINC
+.equ	PINC6	=6
+.equ	PINC5	=5
+.equ	PINC4	=4
+.equ	PINC3	=3
+.equ	PINC2	=2
+.equ	PINC1	=1
+.equ	PINC0	=0
+
+;PORTD
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+;DDRD
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+;PIND
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+;UCSRA
+.equ	RXC	=7
+.equ	TXC	=6
+.equ	UDRE	=5
+.equ	FE	=4
+.equ	OR	=3		; old name kept for compatibilty
+.equ	DOR	=3
+.equ	UPE	=2
+.equ	PE	=2
+.equ	U2X	=1
+.equ	MPCM	=0
+
+;UCSRB
+.equ	RXCIE	=7
+.equ	TXCIE	=6
+.equ	UDRIE	=5
+.equ	RXEN	=4
+.equ	TXEN	=3
+.equ	CHR9	=2		; old name kept for compatibilty
+.equ	UCSZ2	=2
+.equ	RXB8	=1
+.equ	TXB8	=0
+
+;UCSRC
+.equ	URSEL	=7
+.equ	UMSEL	=6
+.equ	UPM1	=5
+.equ	UPM0	=4
+.equ	USBS	=3
+.equ	UCSZ1	=2
+.equ	UCSZ0	=1
+.equ	UCPOL	=0
+		
+;SPCR
+.equ	SPIE	=7
+.equ	SPE	=6
+.equ	DORD	=5
+.equ	MSTR	=4
+.equ	CPOL	=3
+.equ	CPHA	=2
+.equ	SPR1	=1
+.equ	SPR0	=0
+
+;SPSR
+.equ	SPIF	=7
+.equ	WCOL	=6
+.equ	SPI2X	=0
+
+;ACSR
+.equ	ACD	=7
+.equ    ACBG    =6
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIC	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX3    =3
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+; TWCR
+.equ    TWINT   =7
+.equ    TWEA    =6
+.equ    TWSTA   =5
+.equ    TWSTO   =4
+.equ    TWWC    =3
+.equ    TWEN    =2
+
+.equ    TWIE    =0
+
+; TWAR
+.equ    TWA6    =7
+.equ    TWA5    =6
+.equ    TWA4    =5
+.equ    TWA3    =4
+.equ    TWA2    =3
+.equ    TWA1    =2
+.equ    TWA0    =1
+.equ    TWGCE   =0
+
+; TWSR
+.equ    TWS7    =7
+.equ    TWS6    =6
+.equ    TWS5    =5
+.equ    TWS4    =4
+.equ    TWS3    =3
+.equ	TWPS1	=1
+.equ	TWPS0	=0
+
+;ASSR
+.equ    AS2     =3
+.equ    TCN2UB  =2
+.equ    OCR2UB  =1
+.equ    TCR2UB  =0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ 	RAMEND =$45F
+.equ	FLASHEND =$FFF
+
+						;  byte groups
+						;  /\/--\/--\/--\ 
+.equ 	SMALLBOOTSTART	=0b00111110000000  ;($0F80) smallest boot block is 256
+.equ 	SECONDBOOTSTART	=0b00111100000000  ;($0F00) 2'nd boot block size is 512
+.equ 	THIRDBOOTSTART	=0b00111000000000  ;($0E00) third boot block size is 1K
+.equ 	LARGEBOOTSTART	=0b00110000000000  ;($0C00) largest boot block is 2K
+.equ 	BOOTSTART		=THIRDBOOTSTART  ;OBSOLETE!!! kept for compatibility
+.equ	PAGESIZE		=32     ;number of WORDS in a page
+
+.equ	INT0addr=$001	; External Interrupt0 Vector Address
+.equ	INT1addr=$002	; External Interrupt1 Vector Address
+.equ	OC2addr =$003	; Output Compare2 Interrupt Vector Address
+.equ	OVF2addr=$004	; Overflow2 Interrupt Vector Address
+.equ	ICP1addr=$005	; Input Capture1 Interrupt Vector Address
+.equ	OC1Aaddr=$006	; Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr=$007	; Output Compare1B Interrupt Vector Address
+.equ	OVF1addr=$008	; Overflow1 Interrupt Vector Address
+.equ	OVF0addr=$009	; Overflow0 Interrupt Vector Address
+.equ	SPIaddr =$00a	; SPI Interrupt Vector Address
+.equ	URXCaddr=$00b	; USART Receive Complete Interrupt Vector Address
+.equ	UDREaddr=$00c	; USART Data Register Empty Interrupt Vector Address
+.equ	UTXCaddr=$00d	; USART Transmit Complete Interrupt Vector Address
+.equ	ADCCaddr=$00e	; ADC Interrupt Vector Address
+.equ	ERDYaddr=$00f	; EEPROM Interrupt Vector Address
+.equ	ACIaddr =$010	; Analog Comparator Interrupt Vector Address
+.equ    TWIaddr =$011   ; Irq. vector address for Two-Wire Interface
+.equ	SPMaddr =$012	; SPM complete Interrupt Vector Address
+.equ	SPMRaddr =$012	; SPM complete Interrupt Vector Address
diff --git a/include/tn11def.inc b/include/tn11def.inc
new file mode 100644
index 0000000..fe816e9
--- /dev/null
+++ b/include/tn11def.inc
@@ -0,0 +1,126 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"tn11def.inc"
+;* Title		:Register/Bit Definitions for the ATtiny11
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	:avr@atmel.com
+;* Target MCU		:ATtiny11
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the two registers forming the data pointers Z have been 
+;* assigned names ZL - ZH. 
+;*
+;* The Register names are represented by their hexadecimal addresses.
+;*
+;* The Register Bit names are represented by their bit number (0-7).
+;*
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;*
+;* in r16,PORTB  ;read PORTB latch
+;* sbr r16,(1<<PB2)+(1<<PB1) ;set PB2 and PB1 (use masks, not bit#)
+;* out  PORTB,r16  ;output to PORTB
+;*
+;* in r16,TIFR  ;read the Timer Interrupt Flag Register
+;* sbrc r16,TOV0  ;test the overflow flag (use bit#)
+;* rjmp TOV0_is_set  ;jump if set
+;* ...    ;otherwise do something else
+;***************************************************************************
+
+
+
+;***** Specify Device
+.device ATtiny11
+
+;***** I/O Register Definitions
+.equ    SREG    =$3f
+.equ    GIMSK   =$3b
+.equ    GIFR    =$3a
+.equ    TIMSK   =$39
+.equ    TIFR    =$38
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ    TCCR0   =$33
+.equ    TCNT0   =$32
+.equ    WDTCR   =$21
+.equ    PORTB   =$18
+.equ    DDRB    =$17
+.equ    PINB    =$16
+.equ    ACSR    =$08
+
+
+;***** Bit Definitions
+
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+.equ    INT0    =6
+.equ    PCIE    =5
+
+.equ    INTF0   =6
+.equ    PCIF    =5
+
+.equ    TOIE0   =1
+
+.equ    TOV0    =1
+
+.equ    SE      =5
+.equ    SM      =4
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+.equ    CS02    =2
+.equ    CS01    =1
+.equ    CS00    =0
+
+.equ    WDTOE	=4
+.equ    WDE	=3
+.equ    WDP2	=2
+.equ    WDP1	=1
+.equ    WDP0	=0
+
+.equ    ACD     =7
+.equ    ACO     =5
+.equ    ACI     =4
+.equ    ACIE    =3
+.equ    ACIS1   =1
+.equ    ACIS0   =0
+
+.equ    PB4     =4
+.equ    PB3     =3
+.equ    PB2     =2
+.equ    PB1     =1
+.equ    PB0     =0
+
+.equ    DDB4    =4
+.equ    DDB3    =3
+.equ    DDB2    =2
+.equ    DDB1    =1
+.equ    DDB0    =0
+
+.equ    PINB5   =5
+.equ    PINB4   =4
+.equ    PINB3   =3
+.equ    PINB2   =2
+.equ    PINB1   =1
+.equ    PINB0   =0
+
+.def    ZL      =R30
+.def    ZH      =R31
+
+.equ	FLASHEND=$1FF
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	PCINTaddr=$002	;Pin change Interrupt Vector Address
+.equ	OVF0addr=$003	;Overflow0 Interrupt Vector Address
+.equ	ACIaddr =$004	;Analog Comparator Interrupt Vector Address
+
diff --git a/include/tn12def.inc b/include/tn12def.inc
new file mode 100644
index 0000000..555628c
--- /dev/null
+++ b/include/tn12def.inc
@@ -0,0 +1,148 @@
+
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number               :AVR000
+;* File Name            :"tn12.inc"
+;* Title                :Register/Bit Definitions for the ATtiny12
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone    :+47 72 88 43 88 (ATMEL Norway)
+;* Support fax          :+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail       :avr@atmel.com
+;* Target MCU           :ATtiny12
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register      
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the two registers forming the data pointer Z have been 
+;* assigned names ZL - ZH. 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in   r16,PORTB               ;read PORTB latch
+;* sbr  r16,(1<<PB6)+(1<<PB5)   ;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16               ;output to PORTB
+;*
+;* in   r16,TIFR                ;read the Timer Interrupt Flag Register
+;* sbrc r16,TOV0                ;test the overflow flag (use bit#)
+;* rjmp TOV0_is_set             ;jump if set
+;* ...                          ;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATtiny12
+
+;***** I/O Register Definitions
+.equ    SREG    =$3f
+.equ    GIMSK   =$3b
+.equ    GIFR    =$3a
+.equ    TIMSK   =$39
+.equ    TIFR    =$38
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ    TCCR0   =$33
+.equ    TCNT0   =$32
+.equ    OSCCAL  =$31
+.equ    WDTCR   =$21
+.equ    EEAR    =$1e
+.equ    EEDR    =$1d
+.equ    EECR    =$1c
+.equ    PORTB   =$18
+.equ    DDRB    =$17
+.equ    PINB    =$16
+.equ    ACSR    =$08
+
+;***** Bit Definitions
+.equ    INT0    =6
+.equ    PCIE    =5
+
+.equ    INTF0   =6
+.equ    PCIF    =5
+
+.equ    TOIE0   =1
+
+.equ    TOV0    =1
+
+.equ    CS02    =2
+.equ    CS01    =1
+.equ    CS00    =0
+
+.equ    PUD     =6
+.equ    SE      =5
+.equ    SM      =4
+.equ    ISC01   =1
+.equ    ISC00   =0
+
+.equ    WDDE    =4
+.equ    WDE     =3
+.equ    WDP2    =2
+.equ    WDP1    =1
+.equ    WDP0    =0
+
+.equ    CAL7    =7
+.equ    CAL6    =6
+.equ    CAL5    =5
+.equ    CAL4    =4
+.equ    CAL3    =3
+.equ    CAL2    =2
+.equ    CAL1    =1
+.equ    CAL0    =0
+
+.equ    EERIE   =3
+.equ    EEMWE   =2
+.equ    EEWE    =1
+.equ    EERE    =0
+
+.equ    PB4     =4
+.equ    PB3     =3
+.equ    PB2     =2
+.equ    PB1     =1
+.equ    PB0     =0
+
+.equ    DDB5    =5
+.equ    DDB4    =4
+.equ    DDB3    =3
+.equ    DDB2    =2
+.equ    DDB1    =1
+.equ    DDB0    =0
+
+.equ    PINB5   =5
+.equ    PINB4   =4
+.equ    PINB3   =3
+.equ    PINB2   =2
+.equ    PINB1   =1
+.equ    PINB0   =0
+
+.equ    ACD     =7
+.equ    AINBG   =6
+.equ    ACO     =5
+.equ    ACI     =4
+.equ    ACIE    =3
+.equ    ACIS1   =1
+.equ    ACIS0   =0
+
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+.def    ZL      =r30
+.def    ZH      =r31
+
+.equ	FLASHEND=$1FF
+.equ	E2END	=$3F
+
+.equ    INT0addr=$001   ;External Interrupt0 Vector Address
+.equ    PCINTaddr=$002  ;Pin change Interrupt Vector Address
+.equ    OVF0addr=$003   ;Overflow0 Interrupt Vector Address
+.equ    ERDYaddr =$004  ;EEPROM Interrupt Vector Address
+.equ    ACIaddr =$005   ;Analog Comparator Interrupt Vector Address
+
diff --git a/include/tn15def.inc b/include/tn15def.inc
new file mode 100644
index 0000000..405d8d2
--- /dev/null
+++ b/include/tn15def.inc
@@ -0,0 +1,207 @@
+;    Last change:  TF    8 Sep 99    8:18 pm
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;*
+;* Number            : AVR000
+;* File Name         : "T15def.inc"
+;* Title             : Register/Bit Definitions for the ATtiny15
+;* Date              : 1999.09.08
+;* Version           : 1.00
+;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
+;* Support fax       : +47 72 88 43 99 (ATMEL Norway)
+;* Support E-Mail    : avr@atmel.com
+;* Target MCU        : ATtiny15
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;*
+;* The Register names are represented by their hexadecimal addresses.
+;*
+;* The Register Bit names are represented by their bit number (0-7).
+;*
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;*
+;* in    r16,PORTB       ;read PORTB latch
+;* sbr    r16,(1<<PB6)+(1<<PB5)    ;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16        ;output to PORTB
+;*
+;* in      r16,TIFR      ;read the Timer Interrupt Flag Register
+;* sbrc    r16,TOV0      ;test the overflow flag (use bit#)
+;* rjmp    TOV0_is_set   ;jump if set
+;* ...                   ;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATtiny15
+
+;***** I/O Register Definitions
+.equ    SREG    =$3F
+.equ    SPL     =$3D ; ICE only !!!!!!
+.equ    GIMSK   =$3B
+.equ    GIFR    =$3A
+.equ    TIMSK   =$39
+.equ    TIFR    =$38
+.equ    MCUCR   =$35
+.equ    MCUSR   =$34
+.equ    TCCR0   =$33
+.equ    TCNT0   =$32
+.equ    OSCCAL  =$31
+.equ    TCCR1   =$30
+.equ    TCNT1   =$2F
+.equ    OCR1A   =$2E
+.equ    OCR1B   =$2D
+.equ    SFIOR   =$2C
+.equ    WDTCR   =$21
+.equ    EEAR    =$1E
+.equ    EEDR    =$1D
+.equ    EECR    =$1C
+.equ    PORTB   =$18
+.equ    DDRB    =$17
+.equ    PINB    =$16
+.equ    ACSR    =$08
+.equ    ADMUX   =$07
+.equ    ADCSR   =$06
+.equ    ADCH    =$05
+.equ    ADCL    =$04
+
+
+;***** Bit Definitions
+
+; GIMSK
+.equ    INT0    =6
+.equ    PCIE    =5
+
+; GIFR
+.equ    INTF0   =6
+.equ    PCIF    =5
+
+; TIMSK
+.equ    OCIE1   =6
+.equ    TOIE1   =2
+.equ    TOIE0   =1
+
+; TIFR
+.equ    OCF1    =6
+.equ    TOV1    =2
+.equ    TOV0    =1
+
+; MCUCR
+
+.equ    PUD     =6
+.equ	SE	=5
+.equ	SM	=4
+.equ	SM1	=4
+.equ	SM0	=3
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+; MCUSR
+.equ    WDRF    =3
+.equ    BORF    =2
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+; TCCR0
+.equ    CS02    =2
+.equ    CS01    =1
+.equ    CS00    =0
+
+; TCCR1
+.equ    CTC1    =7
+.equ    PWM1    =6
+.equ    COM1A1  =5
+.equ    COM1A0  =4
+.equ    CS13    =3
+.equ    CS12    =2
+.equ    CS11    =1
+.equ    CS10    =0
+
+; WDTCR
+.equ    WDTOE   =4
+.equ    WDE     =3
+.equ    WDP2    =2
+.equ    WDP1    =1
+.equ    WDP0    =0
+
+; EECR
+.equ    EERIE   =3
+.equ    EEMWE   =2
+.equ    EEWE    =1
+.equ    EERE    =0
+
+; PORTB
+.equ    PB4     =4
+.equ    PB3     =3
+.equ    PB2     =2
+.equ    PB1     =1
+.equ    PB0     =0
+
+; DDRB
+.equ    DDB5    =5
+.equ    DDB4    =4
+.equ    DDB3    =3
+.equ    DDB2    =2
+.equ    DDB1    =1
+.equ    DDB0    =0
+
+; PINB
+.equ    PINB5   =5
+.equ    PINB4   =4
+.equ    PINB3   =3
+.equ    PINB2   =2
+.equ    PINB1   =1
+.equ    PINB0   =0
+
+; ACSR
+.equ    ACD     =7
+.equ    AINBG6  =6
+.equ    ACO     =5
+.equ    ACI     =4
+.equ    ACIE    =3
+.equ    ACIS1   =1
+.equ    ACIS0   =0
+
+; ADMUX
+.equ    REFS1   =7
+.equ    REFS0   =6
+.equ    ADLAR   =5
+.equ    MUX2    =2
+.equ    MUX1    =1
+.equ    MUX0    =0
+
+;ADCSR
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+;SFIOR
+.equ    FOC1A   =2
+.equ    PSR1    =1
+.equ    PSR0    =0
+
+.equ    RAMEND  =0       ; Last On-Chip SRAM Location
+.equ    XRAMEND =0       ; Last External RAM Location
+.equ    E2END   =3F      ; Last EEPROM Location
+.equ    FLASHEND=1FF     ; Last FLASH Location
+
+.equ    INT0addr=$001    ; External Interrupt0 Vector Address
+.equ    PCaddr  =$002    ; Pin Change Interrupt Vector Address
+.equ    T1CPaddr=$003    ; Timer1 Compare Interrupt Vector Address
+.equ    T1OVaddr=$004    ; Timer1 Overflow Interrupt Vector Address
+.equ    T0OVaddr=$005    ; Timer0 Overflow Interrupt Vector Address
+.equ    ERDYaddr=$006    ; EEPROM Ready Interrupt Vector Address
+.equ    ACaddr  =$007    ; Analog Comparator Interrupt Vector Address
+.equ    ADCaddr =$008    ; AD Converter Interrupt Vector Address
+
+.def    ZL      =r30
+.def    ZH      =r31
+
diff --git a/include/tn22def.inc b/include/tn22def.inc
new file mode 100644
index 0000000..c1e5259
--- /dev/null
+++ b/include/tn22def.inc
@@ -0,0 +1,123 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"tn22def.inc"
+;* Title		:Register/Bit Definitions for the ATtiny22
+;* Date	 		:99.01.28
+;* Version		:1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-Mail	:avr@atmel.com
+;* Target MCU		:ATtiny22
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* 
+;* The Register names are represented by their hexadecimal addresses.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATtiny22
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	SPL	=$3d
+.equ	GIMSK	=$3b
+.equ	GIFR	=$3a
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	WDTCR	=$21
+.equ	EEAR	=$1e
+.equ	EEARL	=$1e
+.equ	EEDR	=$1d
+.equ	EECR	=$1c
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+
+;***** Bit Definitions
+
+.equ	EXTRF	=1
+.equ	PORF	=0
+
+.equ	INT0	=6
+.equ	INTF0	=6
+
+.equ	TOIE0	=1
+.equ	TOV0	=1
+
+.equ	SE	=5
+.equ	SM	=4
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+.equ	PB4	=4
+.equ	PB3	=3
+.equ	PB2	=2
+.equ	PB1	=1
+.equ	PB0	=0
+
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.def	XL	=r26
+.def	XH	=r27
+.def	YL	=r28
+.def	YH	=r29
+.def	ZL	=r30
+.def	ZH	=r31
+
+.equ    RAMEND  =$DF    ;Last On-Chip SRAM Location
+.equ	XRAMEND =$DF
+.equ	E2END	=$7F
+.equ	FLASHEND=$3FF
+
+
+.equ	INT0addr=$001	;External Interrupt0 Vector Address
+.equ	OVF0addr=$002	;Overflow0 Interrupt Vector Address
+
diff --git a/include/tn26def.inc b/include/tn26def.inc
new file mode 100644
index 0000000..33a81d0
--- /dev/null
+++ b/include/tn26def.inc
@@ -0,0 +1,322 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number				:AVR000
+;* File Name			:"tiny26def.inc"
+;* Title				:Register/Bit Definitions for the ATtiny26
+;* Date                 :April 16th, 2002
+;* Version              :1.00
+;* Support telephone	:+47 72 88 87 20 (ATMEL Norway)
+;* Support fax			:+47 72 88 87 18 (ATMEL Norway)
+;* Support E-mail		:support@atmel.no
+;* Target MCU			:ATtiny26
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register	
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the six registers forming the three data pointers X, Y and
+;* Z have been assigned names XL - ZH. Highest RAM address for Internal 
+;* SRAM is also defined 
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB				;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16				;output to PORTB
+;*
+;* in	r16,TIFR				;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0				;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set				;jump if set
+;* ...							;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATtiny26
+
+;***** I/O Register Definitions
+.equ	SREG	=$3F
+.equ	SP		=$3D
+.equ	GIMSK	=$3B
+.equ	GIFR	=$3A
+.equ	TIMSK	=$39
+.equ	TIFR	=$38
+.equ	MCUCR	=$35
+.equ	MCUSR	=$34
+.equ	TCCR0	=$33
+.equ	TCNT0	=$32
+.equ	OSCCAL	=$31
+.equ	TCCR1A	=$30
+.equ	TCCR1B	=$2F
+.equ	TCNT1	=$2E
+.equ	OCR1A	=$2D
+.equ	OCR1B	=$2C
+.equ	OCR1C	=$2B
+.equ	PLLCSR	=$29
+.equ	WDTCR	=$21
+.equ	EEAR	=$1E
+.equ	EEDR	=$1D
+.equ	EECR	=$1C
+.equ	PORTA	=$1B
+.equ	DDRA	=$1A
+.equ	PINA	=$19
+.equ	PORTB	=$18
+.equ	DDRB	=$17
+.equ	PINB	=$16
+.equ	USIDR	=$0F
+.equ	USISR	=$0E
+.equ	USICR	=$0D
+.equ	ACSR	=$08
+.equ	ADMUX	=$07
+.equ	ADCSR	=$06
+.equ	ADCH	=$05
+.equ	ADCL	=$04
+
+;***** Bit Definitions
+;***** GIMSK *****
+.equ	INT0	=6
+.equ	PCIE1	=5
+.equ	PCIE0	=4
+
+;***** GIFR ******
+.equ	INTF0	=6
+.equ	PCIF	=5
+
+;***** TIMSK *****
+.equ	OCIE1A	=6
+.equ	OCIE1B	=5
+.equ	TOIE1	=2
+.equ	TOIE0	=1
+
+;***** TIFR ******
+.equ	OCF1A	=6
+.equ	OCF1B	=5
+.equ	TOV1 	=2
+.equ	TOV0	=1
+
+;***** MCUCR ***** 
+.equ 	PUD 	=6
+.equ	SE	=5
+.equ	SM1	=4
+.equ	SM0	=3
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+;***** MCUSR ***** 
+.equ	WDRF 	=3
+.equ	BORF 	=2
+.equ	EXTRF	=1
+.equ	PORF 	=0
+
+;***** TCCR0 *****
+.equ	PSR0	=3
+.equ	CS02 	=2
+.equ	CS01 	=1
+.equ	CS00 	=0
+
+;***** OSCCAL ****
+.equ	OSCCAL4	=4
+.equ	OSCCAL3	=3
+.equ	OSCCAL2	=2
+.equ	OSCCAL1	=1
+.equ	OSCCAL0	=0
+
+;***** TCCR1A ****
+.equ	COM1A1	=7
+.equ    COM1A0	=6
+.equ    COM1B1	=5
+.equ    COM1B0	=4
+.equ	FOC1A	=3
+.equ    FOC1B   =2
+.equ	PWM1A	=1
+.equ	PWM1B	=0
+
+;***** TCCR1B **** 
+.equ	CTC1 	=7
+.equ	PSR1 	=6
+.equ	CS13 	=3
+.equ	CS12 	=2
+.equ	CS11 	=1
+.equ	CS10 	=0
+
+;***** PLLCSR ****
+.equ	PCKE	=2
+.equ	PLLE	=1
+.equ	PLOCK	=0
+
+;***** WDTCR *****
+.equ	WDCE	=4
+.equ	WDE		=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+;***** EEAR ******
+.equ	EEAR6	=6
+.equ	EEAR5	=5
+.equ	EEAR4	=4
+.equ	EEAR3	=3
+.equ	EEAR2	=2
+.equ	EEAR1	=1
+.equ	EEAR0	=0
+
+;***** EECR ******
+.equ	EERIE	=3
+.equ	EEMWE	=2
+.equ	EEWE	=1
+.equ	EERE	=0
+
+;***** PORTA ***** 
+.equ	PA7		=7
+.equ	PA6		=6
+.equ	PA5		=5
+.equ	PA4		=4
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+.equ	PORTA7	=7
+.equ	PORTA6	=6
+.equ	PORTA5	=5
+.equ	PORTA4	=4
+.equ	PORTA3	=3
+.equ	PORTA2	=2
+.equ	PORTA1	=1
+.equ	PORTA0	=0
+
+;***** DDRA ******
+.equ	DDA7	=7
+.equ	DDA6	=6
+.equ	DDA5	=5
+.equ	DDA4	=4
+.equ	DDA3	=3
+.equ	DDA2	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+;***** PINA ******
+.equ	PINA7	=7
+.equ	PINA6	=6
+.equ	PINA5	=5
+.equ	PINA4	=4
+.equ	PINA3	=3
+.equ	PINA2	=2
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+;***** PORTB ***** 
+.equ	PB7		=7
+.equ	PB6		=6
+.equ	PB5		=5
+.equ	PB4		=4
+.equ	PB3		=3
+.equ	PB2		=2
+.equ	PB1		=1
+.equ	PB0		=0
+
+.equ	PORTB7	=7
+.equ	PORTB6	=6
+.equ	PORTB5	=5
+.equ	PORTB4	=4
+.equ	PORTB3	=3
+.equ	PORTB2	=2
+.equ	PORTB1	=1
+.equ	PORTB0	=0
+
+;***** DDRB ******
+.equ	DDB7	=7
+.equ	DDB6	=6
+.equ	DDB5	=5
+.equ	DDB4	=4
+.equ	DDB3	=3
+.equ	DDB2	=2
+.equ	DDB1	=1
+.equ	DDB0	=0
+
+;***** PINB ******
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+;***** USISR *****
+.equ	USISIF	=7
+.equ	USIOIF	=6
+.equ	USIPF	=5
+.equ	USIDC	=4
+.equ	USICNT3	=3
+.equ    USICNT2 =2
+.equ    USICNT1 =1
+.equ    USICNT0 =0
+
+;***** USICR *****
+.equ    USISIE   =7
+.equ    USIOIE  =6
+.equ	USIWM1	=5
+.equ	USIWM0	=4
+.equ	USICS1	=3
+.equ	USICS0	=2
+.equ	USICLK	=1
+.equ	USITC	=0
+
+;***** ACSR ******
+.equ	ACD		=7
+.equ	ACBG	=6
+.equ	ACO		=5
+.equ	ACI		=4
+.equ	ACIE	=3
+.equ	ACME	=2
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+;***** ADMUX *****
+.equ	REFS1	=7
+.equ	REFS0	=6
+.equ	ADLAR	=5
+.equ	MUX4	=4
+.equ	MUX3	=3
+.equ	MUX2	=2
+.equ	MUX1 	=1
+.equ	MUX0 	=0
+
+;***** ADCSR *****
+.equ    ADEN    =7
+.equ    ADSC    =6
+.equ    ADFR    =5
+.equ    ADIF    =4
+.equ    ADIE    =3
+.equ    ADPS2   =2
+.equ    ADPS1   =1
+.equ    ADPS0   =0
+
+.def	XL		=r26
+.def	XH		=r27
+.def	YL		=r28
+.def	YH		=r29
+.def	ZL		=r30
+.def	ZH		=r31
+
+.equ 	RAMEND =$DF
+
+.equ	INT0addr	=$001	;External Interrupt0 Vector Address
+.equ	IOPINSaddr	=$002	;Pin change interrupt
+.equ	OC1Aaddr	=$003	;Output Compare1A Interrupt Vector Address
+.equ	OC1Baddr	=$004	;Output Compare1B Interrupt Vector Address
+.equ	OVF1addr	=$005	;Overflow1 Interrupt Vector Address
+.equ	OVF0addr	=$006	;Overflow0 Interrupt Vector Address
+.equ	USI_STARTaddr	=$007	;Universal Seria Bus Start Interrupt Address
+.equ	USI_OVFaddr	=$008	;Universal Seria Bus Overflow Interrupt Address
+.equ	ERDYaddr	=$009	;EEPROM Ready Interrupt Vector Address
+.equ	ACIaddr 	=$00A	;Analog Comparator Interrupt Vector Address
+.equ	ADCCaddr 	=$00B	;ADC conversion complete Interrupt Vector Address
diff --git a/include/tn28def.inc b/include/tn28def.inc
new file mode 100644
index 0000000..f9beb00
--- /dev/null
+++ b/include/tn28def.inc
@@ -0,0 +1,184 @@
+;***************************************************************************
+;* A P P L I C A T I O N   N O T E   F O R   T H E   A V R   F A M I L Y
+;* 
+;* Number		:AVR000
+;* File Name		:"tn28def.inc"
+;* Title		:Register/Bit Definitions for the ATtiny28
+;* Date                 :99.01.28
+;* Version              :1.30
+;* Support telephone	:+47 72 88 43 88 (ATMEL Norway)
+;* Support fax		:+47 72 88 43 99 (ATMEL Norway)
+;* Support E-mail	:avr@atmel.com
+;* Target MCU		:ATtiny28
+;*
+;* DESCRIPTION
+;* When including this file in the assembly program file, all I/O register
+;* names and I/O register bit names appearing in the data book can be used.
+;* In addition, the two registers forming the data pointers Z have been 
+;* assigned names ZL - ZH. 
+;*
+;*
+;* The Register names are represented by their hexadecimal address.
+;* 
+;* The Register Bit names are represented by their bit number (0-7).
+;* 
+;* Please observe the difference in using the bit names with instructions
+;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" 
+;* (skip if bit in register set/cleared). The following example illustrates
+;* this:
+;* 
+;* in	r16,PORTB		;read PORTB latch
+;* sbr	r16,(1<<PB6)+(1<<PB5)	;set PB6 and PB5 (use masks, not bit#)
+;* out  PORTB,r16		;output to PORTB
+;*
+;* in	r16,TIFR		;read the Timer Interrupt Flag Register
+;* sbrc	r16,TOV0		;test the overflow flag (use bit#)
+;* rjmp	TOV0_is_set		;jump if set
+;* ...				;otherwise do something else
+;***************************************************************************
+
+;***** Specify Device
+.device ATtiny28
+
+;***** I/O Register Definitions
+.equ	SREG	=$3f
+.equ	PORTA	=$1b
+.equ	PACR	=$1a
+.equ	PINA	=$19
+.equ	PINB	=$16
+.equ	PORTD	=$12
+.equ	DDRD	=$11
+.equ	PIND	=$10
+.equ	ACSR	=$08
+.equ	MCUCS	=$07
+.equ    ICR     =$06
+.equ    IFR     =$05
+.equ	TCCR0	=$04
+.equ	TCNT0	=$03
+.equ	MODCR	=$02
+.equ	WDTCR	=$01
+.equ	OSCCAL	=$00
+
+
+;***** Bit Definitions
+.equ	PA3		=3
+.equ	PA2		=2
+.equ	PA1		=1
+.equ	PA0		=0
+
+.equ	DDA3	=3
+.equ	PA2HC	=2
+.equ	DDA1	=1
+.equ	DDA0	=0
+
+.equ	PINA3	=3
+.equ	PINA1	=1
+.equ	PINA0	=0
+
+.equ	PINB7	=7
+.equ	PINB6	=6
+.equ	PINB5	=5
+.equ	PINB4	=4
+.equ	PINB3	=3
+.equ	PINB2	=2
+.equ	PINB1	=1
+.equ	PINB0	=0
+
+.equ	PD7	=7
+.equ	PD6	=6
+.equ	PD5	=5
+.equ	PD4	=4
+.equ	PD3	=3
+.equ	PD2	=2
+.equ	PD1	=1
+.equ	PD0	=0
+
+.equ	DDD7	=7
+.equ	DDD6	=6
+.equ	DDD5	=5
+.equ	DDD4	=4
+.equ	DDD3	=3
+.equ	DDD2	=2
+.equ	DDD1	=1
+.equ	DDD0	=0
+
+.equ	PIND7	=7
+.equ	PIND6	=6
+.equ	PIND5	=5
+.equ	PIND4	=4
+.equ	PIND3	=3
+.equ	PIND2	=2
+.equ	PIND1	=1
+.equ	PIND0	=0
+
+.equ	ACD	=7
+.equ	ACO	=5
+.equ	ACI	=4
+.equ	ACIE	=3
+.equ	ACIS1	=1
+.equ	ACIS0	=0
+
+.equ	PLUPB	=7
+.equ	SE	=5
+.equ	SM	=4
+.equ    WDRF    =3
+.equ    EXTRF   =1
+.equ    PORF    =0
+
+.equ	INT1	=7
+.equ	INT0	=6
+.equ	LLIE	=5
+.equ	TOIE0	=4
+.equ	ISC11	=3
+.equ	ISC10	=2
+.equ	ISC01	=1
+.equ	ISC00	=0
+
+.equ	INTF1	=7
+.equ	INTF0	=6
+.equ	TOV0	=4
+
+.equ	FOV0	=7
+.equ	OOM01	=4
+.equ	OOM00	=3
+.equ	CS02	=2
+.equ	CS01	=1
+.equ	CS00	=0
+
+.equ	WDTOE	=4
+.equ	WDE	=3
+.equ	WDP2	=2
+.equ	WDP1	=1
+.equ	WDP0	=0
+
+.equ    ONTIM4  =7
+.equ    ONTIM3  =6
+.equ    ONTIM2  =5
+.equ    ONTIM1  =4
+.equ    ONTIM0  =3
+.equ    MCONF2  =2
+.equ    MCONF1  =1
+.equ    MCONF0  =0
+
+.equ	CAL7	=7
+.equ	CAL6	=6
+.equ	CAL5	=5
+.equ	CAL4	=4
+.equ	CAL3	=3
+.equ	CAL2	=2
+.equ	CAL1	=1
+.equ	CAL0	=0
+
+.def	ZL	=r30
+.def	ZH	=r31
+
+
+.equ	FLASHEND = 0x07FF
+.equ	RAMEND   = 0x03FF
+
+.equ	INT0addr =$001	;External Interrupt0 Vector Address
+.equ	INT1addr =$002	;External Interrupt1 Vector Address
+.equ	LLINTaddr=$003	;Low level Interrupt Vector Address
+.equ	OVF0addr =$004	;Overflow0 Interrupt Vector Address
+.equ	ACIaddr  =$005	;Analog Comparator Interrupt Vector Address
+