added fx2 rule to Makefile

[my-code/fpga.git] / fx2 / fx2.c

diff --git a/fx2/fx2.c b/fx2/fx2.c
index aa8d4cb..6b2fe21 100644 (file)
--- a/fx2/fx2.c
+++ b/fx2/fx2.c
@@ -21,29 +21,71 @@ typedef unsigned char u8;
 typedef unsigned short u16;
 typedef unsigned int u32;
 
-/* fx2 register */
+/*
+ * fx2 register
+ */
+
+/* general configuration */
+xdata at 0xe600 volatile u8 CPUCS;
+xdata at 0xe601 volatile u8 IFCONFIG;
+
+/* endpoint configuration */
+xdata at 0xe60b volatile u8 REVCTL;
+xdata at 0xe612 volatile u8 EP2CFG;
+xdata at 0xe614 volatile u8 EP6CFG;
+xdata at 0xe618 volatile u8 EP2FIFOCFG;
+xdata at 0xe619 volatile u8 EP4FIFOCFG;
+xdata at 0xe61a volatile u8 EP6FIFOCFG;
+xdata at 0xe61b volatile u8 EP8FIFOCFG;
+
+/* special funtion registers */
 sfr at 0xb5 OED;
 sfr at 0xb0 IOD;
 
+/* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
+ * and some others (p. 438).
+ * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
+#define SYNCDELAY _asm \
+       nop; nop; nop; nop; nop; nop; nop; nop; \
+       nop; nop; nop; nop; nop; nop; nop; nop; \
+       nop; _endasm
+
 void power_on() {
 
+       /* high level must be applied to the mosfet gate for power on
+        *
+        * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
+        */
+
+       /* configure pin 7 of port d as output */
        OED|=(1<<7);
+
+       /* pull it high */
        IOD|=(1<<7);
 }
 
 void slave_fifo_init() {
 
+       /* initialization of the slave fifo, used by external logic (the fpga)
+        * to do usb communication with the host */
+
        /* set bit 0 and 1 - fifo slave config */       
        IFCONFIG|=0x03;
 
        /* async mode */
        IFCONFIG|=0x04;
 
-       /* 8 bit fifo to all endpoints */
-       EP2FIFOCFG&=^(1<<0);
-       EP4FIFOCFG&=^(1<<0);
-       EP6FIFOCFG&=^(1<<0);
-       EP8FIFOCFG&=^(1<<0);
+       /* p. 180: must be set to 1 */
+       REVCTL|=((1<<0)|(1<<1));
+
+       /* 8 bit fifo to all endpoints
+        *
+        * ('or' of all these bits define port d functionality)
+        */
+       EP2FIFOCFG&=~(1<<0);
+       EP4FIFOCFG&=~(1<<0);
+       EP6FIFOCFG&=~(1<<0);
+       EP8FIFOCFG&=~(1<<0);
 
        /* default indexed flag configuration:
         *
@@ -54,6 +96,46 @@ void slave_fifo_init() {
         * todo: -> fixed configuration
         */
 
+       /* endpoint configuration:
+        *
+        * (assuming 'high bandwidth in' [fpga -> host]
+        *  and 'low bandwidth out' [host->fpga] applications)
+        * 
+        * ep2: bulk in 3x1024
+        * ep6: bulk out 2x512
+        *
+        * 0xeb = 1 1 1 0 1 0 1 1 = bulk in 3x1024
+        * 0xa2 = 1 0 1 0 0 0 1 0 = bulk out 2x512
+        * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
+        */
+       EP2CFG=0xeb;
+       EP4CFG=0x01;
+       EP6CFG=0xa2;
+       EP8CFG=0x01;
+
+       /* reset the fifo */
+       FIFORESET=0x80; /* nak all transfers */
+       FIFORESET=0x02; /* reset ep2 */
+       FIFORESET=0x06; /* reset ep6 */
+       FIFORESET=0x00; /* restore normal operation */
+
+       /* auto in/out, no cpu interaction! auto in len = 1024 */
+       EP2FIFOCFG|=(1<<3);
+       EP2AUTOINLENH=(1<<2);
+       EP2AUTOINLENL=0;
+       EP6FIFOCFG|=(1<<4);
+
+       /* maybe OUTPKTEND necessary (with skip=1) */
+}
+
+void ep1_init() {
+
+       /* initialize endpoint 1 (will be used for jtag) */
+
+       /* endpoint 1 configuration:
+        *
+        * default (valid, bulk) fits!
+        */
 
 }
 
@@ -65,6 +147,7 @@ void fx2_init() {
        /* slave fifo init */
        slave_fifo_init();
 
+       /* ep1_init(); */
 }
 
 void main() {