2 # startup.s - starup code for the lpc2220
4 # author: hackbard@hackdaworld.org
13 .equ sram_size, (64*1024)
14 .equ sram_addr, 0x40000000
15 .equ sram_top, (sram_addr+sram_size-4)
19 .equ stack_size, (4*1024)
20 .equ stack_top, sram_top
21 .equ stack_limit, (sram_top-stack_size)
23 .equ stack_size_fiq, 64
24 .equ stack_size_irq, 256
25 .equ stack_size_supervisor, 64
26 .equ stack_size_abort, 64
27 .equ stack_size_undefined, 64
28 .equ stack_size_system, 1024
30 # arm modes - control bits of the program status register
31 # ref: chapter 2.8, arm7tdmi-s technical reference manual
36 .equ mode_supervisor, 0x13
38 .equ mode_undefined, 0x1b
39 .equ mode_system, 0x1f
41 .equ fiq_disable, 0x40
42 .equ irq_disable, 0x80
51 # exception handling must go to the very beginning
54 b interrupt_handler_undef_instruction
55 b interrupt_handler_soft_ir
56 b interrupt_handler_prefetch_abort
57 b interrupt_handler_data_abort
59 b interrupt_handler_irq
60 b interrupt_handler_fiq
62 # reset handling goes here
66 # init stack pointer for each mode + set stack limit
70 msr cpsr_c, #mode_undefined|irq_disable|fiq_disable
72 sub r0, r0, #stack_size_undefined
74 msr cpsr_c, #mode_abort|irq_disable|fiq_disable
76 sub r0, r0, #stack_size_abort
78 msr cpsr_c, #mode_fiq|irq_disable|fiq_disable
80 sub r0, r0, #stack_size_fiq
82 msr cpsr_c, #mode_irq|irq_disable|fiq_disable
84 sub r0, r0, #stack_size_irq
86 msr cpsr_c, #mode_supervisor|irq_disable|fiq_disable
88 sub r0, r0, #stack_size_supervisor
90 msr cpsr_c, #mode_system|irq_disable|fiq_disable
92 sub r0, r0, #stack_size_system