4 * author: hackbard@hackdaworld.org
7 * - switch on board power (done)
8 * - allow high speed bulk usb transfer
13 /* constant definitions */
16 /* type definitions */
17 typedef unsigned char u8;
18 typedef unsigned short u16;
19 typedef unsigned int u32;
25 /* general configuration */
26 xdata at 0xe600 volatile u8 CPUCS;
27 xdata at 0xe601 volatile u8 IFCONFIG;
29 /* endpoint configuration */
30 xdata at 0xe604 volatile u8 FIFORESET;
31 xdata at 0xe60b volatile u8 REVCTL;
32 xdata at 0xe610 volatile u8 EP1OUTCFG;
33 xdata at 0xe611 volatile u8 EP1INCFG;
34 xdata at 0xe612 volatile u8 EP2CFG;
35 xdata at 0xe613 volatile u8 EP4CFG;
36 xdata at 0xe614 volatile u8 EP6CFG;
37 xdata at 0xe615 volatile u8 EP8CFG;
38 xdata at 0xe618 volatile u8 EP2FIFOCFG;
39 xdata at 0xe619 volatile u8 EP4FIFOCFG;
40 xdata at 0xe61a volatile u8 EP6FIFOCFG;
41 xdata at 0xe61b volatile u8 EP8FIFOCFG;
42 xdata at 0xe620 volatile u8 EP2AUTOINLENH;
43 xdata at 0xe621 volatile u8 EP2AUTOINLENL;
44 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
45 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
47 /* endpoint control/status */
48 xdata at 0xe6a1 volatile u8 EP1OUTCS;
49 xdata at 0xe6a2 volatile u8 EP1INCS;
50 xdata at 0xe68d volatile u16 EP1OUTBC;
51 xdata at 0xe68f volatile u16 EP1INBC;
56 /* access to endpoint buffers */
57 xdata at 0xe780 volatile u8 EP1OUTBUF[64];
58 xdata at 0xe7c0 volatile u8 EP1INBUF[64];
60 /* special funtion registers */
64 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
65 * and some others (p. 438).
66 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
67 #define SYNCDELAY _asm \
68 nop; nop; nop; nop; nop; nop; nop; nop; \
69 nop; nop; nop; nop; nop; nop; nop; nop; \
74 /* pin 7 of port d connected to mosfet gate controlling the board power
76 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
79 /* configure pin 7 of port d as output */
87 /* toggle high/low state of the mosfet gate */
100 /* pin 5 of port d disables tdi -> tdo forward */
105 * tdi - pin 0 (input)
106 * tdo - pin 2 (output)
107 * tms - pin 3 (output)
108 * tck - pin 4 (output)
110 OED|=((1<<2)|(1<<3)|(1<<4));
117 /* cpu initialization: (0x10)
119 * - none inverted signal
128 void slave_fifo_init() {
130 /* initialization of the slave fifo, used by external logic (the fpga)
131 * to do usb communication with the host */
133 /* enable dyn_out and enhanced packet handling (p. 189) */
137 /* internal 48 mhz clock, async, slave fifo */
143 * ep2: bulk out 2x512
144 * ep4: bulk out 2x512
155 FIFORESET=0x80; /* nak all transfers */
157 FIFORESET=0x02; /* reset ep2 */
159 FIFORESET=0x04; /* reset ep4 */
161 FIFORESET=0x06; /* reset ep6 */
163 FIFORESET=0x08; /* reset ep8 */
165 FIFORESET=0x00; /* restore normal operation */
168 /* 8 bit fifo to all endpoints */
178 /* default indexed flag configuration:
180 * flag a: programmable level
184 * todo: -> fixed configuration
187 /* auto in/out, no cpu interaction! auto in len = 512 */
192 EP6AUTOINLENH=(1<<1);
201 /* initialize endpoint 1
203 * used for jtag & control
206 /* endpoint 1 configuration:
208 * default (valid, bulk) fits!
211 /* arm ep1out, clear ep1out and ep1in stall bit */
226 /* power init & power on */
230 /* slave fifo init */
244 /* initialize the fx2 */
247 /* jtag by polling ep1 */
250 if(!(EP1OUTCS&BUSY)) {
253 IOD=(IOD&(~0x1c))|(buf&0x1c);
256 if(!(EP1INCS&BUSY)) {
257 EP1INBUF[0]=IOD&0x01;