4 * author: hackbard@hackdaworld.org
6 * number of priorities:
7 * - switch on board power
8 * - allow high speed usb transfer
13 /* constant definitions */
19 /* type definitions */
20 typedef unsigned char u8;
21 typedef unsigned short u16;
22 typedef unsigned int u32;
28 /* general configuration */
29 xdata at 0xe600 volatile u8 CPUCS;
30 xdata at 0xe601 volatile u8 IFCONFIG;
32 /* endpoint configuration */
33 xdata at 0xe604 volatile u8 FIFORESET;
34 xdata at 0xe60b volatile u8 REVCTL;
35 xdata at 0xe612 volatile u8 EP2CFG;
36 xdata at 0xe613 volatile u8 EP4CFG;
37 xdata at 0xe614 volatile u8 EP6CFG;
38 xdata at 0xe615 volatile u8 EP8CFG;
39 xdata at 0xe618 volatile u8 EP2FIFOCFG;
40 xdata at 0xe619 volatile u8 EP4FIFOCFG;
41 xdata at 0xe61a volatile u8 EP6FIFOCFG;
42 xdata at 0xe61b volatile u8 EP8FIFOCFG;
43 xdata at 0xe624 volatile u8 EP6AUTOINLENH;
44 xdata at 0xe625 volatile u8 EP6AUTOINLENL;
46 /* special funtion registers */
50 /* synchronization delay after writing/reading to registers 0xe600 - 0xe6ff
51 * and some others (p. 438).
52 * maximum delay necessary at highest cpu speed: 16 cycles => 17 nops */
53 #define SYNCDELAY _asm \
54 nop; nop; nop; nop; nop; nop; nop; nop; \
55 nop; nop; nop; nop; nop; nop; nop; nop; \
60 /* high level must be applied to the mosfet gate for power on
62 * ref: http://digilentinc.com/Data/Products/NEXYS/Nexys_sch.pdf
65 /* configure pin 7 of port d as output */
72 void slave_fifo_init() {
74 /* initialization of the slave fifo, used by external logic (the fpga)
75 * to do usb communication with the host */
77 /* set bit 0 and 1 - fifo slave config */
83 /* p. 180: must be set to 1 */
84 REVCTL|=((1<<0)|(1<<1));
86 /* 8 bit fifo to all endpoints
88 * ('or' of all these bits define port d functionality)
95 /* default indexed flag configuration:
97 * flag a: programmable level
101 * todo: -> fixed configuration
104 /* endpoint configuration:
107 * ep6: bulk out 4x512
109 * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
110 * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
111 * 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
119 FIFORESET=0x80; /* nak all transfers */
120 FIFORESET=0x02; /* reset ep2 */
121 FIFORESET=0x06; /* reset ep6 */
122 FIFORESET=0x00; /* restore normal operation */
124 /* auto in/out, no cpu interaction! auto in len = 512 */
127 EP6AUTOINLENH=(1<<1);
130 /* maybe OUTPKTEND necessary (with skip=1) */
135 /* initialize endpoint 1 (will be used for jtag) */
137 /* endpoint 1 configuration:
139 * default (valid, bulk) fits!
146 /* swicth on power */
149 /* slave fifo init */
157 /* initialize the fx2 */