1 ;***************************************************************************
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2 ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 ;* File Name : "m169def.inc"
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6 ;* Title : Register/Bit Definitions for the ATmega169
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7 ;* Date : June 14th, 2001
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9 ;* Support telephone : +47 72 88 43 88 (ATMEL Norway)
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10 ;* Support fax : +47 72 88 43 99 (ATMEL Norway)
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11 ;* Support E-mail : support@atmel.no
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12 ;* Target MCU : ATmega169
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15 ;* When including this file in the assembly program file, all I/O register
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16 ;* names and I/O register bit names appearing in the data book can be used.
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17 ;* In addition, the six registers forming the three data pointers X, Y and
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18 ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 ;* SRAM is also defined
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21 ;* The Register names are represented by their hexadecimal address.
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23 ;* The Register Bit names are represented by their bit number (0-7).
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25 ;* Please observe the difference in using the bit names with instructions
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26 ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 ;* (skip if bit in register set/cleared). The following example illustrates
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30 ;* in r16,PORTB ;read PORTB latch
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31 ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 ;* out PORTB,r16 ;output to PORTB
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34 ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 ;* rjmp TOV0_is_set ;jump if set
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37 ;* ... ;otherwise do something else
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38 ;***************************************************************************
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40 ;**** Specify Device ****
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43 ;*****************************************************************************
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44 ; I/O Register Definitions
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45 ;*****************************************************************************
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47 ;**** Memory Mapped I/O Register Definitions ****
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158 ;*****************************************************************************
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160 ;*****************************************************************************
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162 ; *** LCDDR18, LCDDR13, LCDDR8, LCDDR3 ***
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165 ; *** LCDSR17, LCDSR12, LCDSR7, LCDSR2 ***
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175 ; *** LCDSR16, LCDSR11, LCDSR6, LCDSR1 ***
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185 ; *** LCDSR15, LCDSR10, LCDSR5, LCDSR0 ***
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516 ; To make tim8pwm_def.inc file
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517 ; part independent.
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754 ;*****************************************************************************
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755 ; CPU Register Declarations
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756 ;*****************************************************************************
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758 .def XL = r26 ; X pointer low
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759 .def XH = r27 ; X pointer high
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760 .def YL = r28 ; Y pointer low
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761 .def YH = r29 ; Y pointer high
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762 .def ZL = r30 ; Z pointer low
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763 .def ZH = r31 ; Z pointer high
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766 ;*****************************************************************************
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767 ; Data Memory Declarations
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768 ;*****************************************************************************
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770 .equ RAMEND = $4ff ; Highest internal data memory (SRAM) address.
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771 ;(1k RAM + IO + REG)
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772 .equ EEPROMEND = $01ff ; Highest EEPROM address.
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774 ;*****************************************************************************
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775 ; Program Memory Declarations
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776 ;*****************************************************************************
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778 .equ FLASHEND = $1FFF ; Highest program memory (flash) address
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779 ; (When addressed as 16 bit words)
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780 ; ( 8k words , 16k byte )
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782 ;**** Boot Vectors ****
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785 .equ SMALLBOOTSTART =0b1111110000000 ;($1F80) smallest boot block is 256B
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786 .equ SECONDBOOTSTART =0b1111100000000 ;($1F00) second boot block size is 512B
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787 .equ THIRDBOOTSTART =0b1111000000000 ;($1E00) third boot block size is 1KB
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788 .equ LARGEBOOTSTART =0b1110000000000 ;($1C00) largest boot block is 2KB
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789 .equ BOOTSTART =THIRDBOOTSTART ;OBSOLETE!!! kept for compatibility
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791 ;**** Page Size ****
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792 .equ PAGESIZE =64 ;number of WORDS in a page
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794 ;**** Interrupt Vectors ****
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795 .equ INT0addr =$002 ;External Interrupt0 Interrupt Address
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796 .equ PCINT0addr =$004 ;Pin Change Interrupt0 Interrupt Address
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797 .equ PCINT1addr =$006 ;Pin Change Interrupt1 Interrupt Address
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798 .equ CMP2addr =$008
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799 .equ OC2addr =$008 ;Timer/Counter2 Compare Match Interrupt Address
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800 .equ OVF2addr =$00a ;Overflow1 Interrupt Address
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801 .equ ICP1addr =$00c ;Input Capture1 Interrupt Address
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802 .equ OC1Aaddr =$00e ;Output Compare1A Interrupt Address
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803 .equ OC1Baddr =$010 ;Output Compare1B Interrupt Address
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804 .equ OVF1addr =$012 ;Overflow1 Interrupt Address
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805 .equ CMP0addr =$014
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806 .equ OC0addr =$014 ;Timer/Counter0 Compare Match Interrupt Address
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807 .equ OVF0addr =$016 ;Overflow0 Interrupt Address
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808 .equ SPIaddr =$018 ;SPI Interrupt Address
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809 .equ URXC0addr =$01a ;UART Receive Complete Interrupt Address
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810 .equ UDRE0addr =$01c ;UART Data Register Empty Interrupt Address
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811 .equ UTXC0addr =$01e ;UART Transmit Complete Interrupt Address
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812 .equ USI_STARTaddr=$020 ;Universal Serial Bus Start Interrupt Address
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813 .equ USI_OVFaddr =$022 ;Universal Serial Bus Overflow Interrupt Address
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814 .equ ACIaddr =$024 ;Analog Comparator Interrupt Address
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815 .equ ADCCaddr =$026 ;ADC Conversion Complete Interrupt Address
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816 .equ ERDYaddr =$028 ;EEPROM write complete Interrupt Address
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817 .equ SPMRaddr =$02a ;Store Program Memory Ready Interrupt Address
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818 .equ LCDSFaddr =$02c ;LCD Start of Frame Interrupt Address
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820 ;for compatibility with s8515
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821 .equ URXCaddr=$01a ;UART Receive Complete Interrupt
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822 .equ UDREaddr=$01e ;UART Data Register Empty Interrupt
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823 .equ UTXCaddr=$022 ;UART Transmit Complete Interrupt
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