xdata at 0xe601 volatile u8 IFCONFIG;
/* endpoint configuration */
+xdata at 0xe604 volatile u8 FIFORESET;
xdata at 0xe60b volatile u8 REVCTL;
xdata at 0xe612 volatile u8 EP2CFG;
+xdata at 0xe613 volatile u8 EP4CFG;
xdata at 0xe614 volatile u8 EP6CFG;
+xdata at 0xe615 volatile u8 EP8CFG;
xdata at 0xe618 volatile u8 EP2FIFOCFG;
xdata at 0xe619 volatile u8 EP4FIFOCFG;
xdata at 0xe61a volatile u8 EP6FIFOCFG;
xdata at 0xe61b volatile u8 EP8FIFOCFG;
+xdata at 0xe624 volatile u8 EP6AUTOINLENH;
+xdata at 0xe625 volatile u8 EP6AUTOINLENL;
/* special funtion registers */
sfr at 0xb5 OED;
/* endpoint configuration:
*
- * (assuming 'high bandwidth in' [fpga -> host]
- * and 'low bandwidth out' [host->fpga] applications)
- *
- * ep2: bulk in 3x1024
- * ep6: bulk out 2x512
+ * ep2: bulk in 4x512
+ * ep6: bulk out 4x512
*
- * 0xeb = 1 1 1 0 1 0 1 1 = bulk in 3x1024
- * 0xa2 = 1 0 1 0 0 0 1 0 = bulk out 2x512
+ * 0xa0 = 1 0 1 0 0 0 0 0 = bulk out 4x512
+ * 0xe0 = 1 1 1 0 0 0 0 0 = bulk in 4x512
* 0x01 = 0 0 0 0 0 0 0 1 = invalid (bit,type,buf)
*/
- EP2CFG=0xeb;
+ EP2CFG=0xa0;
EP4CFG=0x01;
- EP6CFG=0xa2;
+ EP6CFG=0xe0;
EP8CFG=0x01;
/* reset the fifo */
FIFORESET=0x06; /* reset ep6 */
FIFORESET=0x00; /* restore normal operation */
- /* auto in/out, no cpu interaction! auto in len = 1024 */
- EP2FIFOCFG|=(1<<3);
- EP2AUTOINLENH=(1<<2);
- EP2AUTOINLENL=0;
- EP6FIFOCFG|=(1<<4);
+ /* auto in/out, no cpu interaction! auto in len = 512 */
+ EP2FIFOCFG|=(1<<4);
+ EP6FIFOCFG|=(1<<3);
+ EP6AUTOINLENH=(1<<1);
+ EP6AUTOINLENL=0;
/* maybe OUTPKTEND necessary (with skip=1) */
}