bullshit commit, sync for travel (to zn00H!) :)

[my-code/arm.git] / betty / startup.s

diff --git a/betty/startup.s b/betty/startup.s
index d6b0184..18006aa 100644 (file)
--- a/betty/startup.s
+++ b/betty/startup.s
@@ -41,6 +41,8 @@
 .equ   fiq_disable,    0x40
 .equ   irq_disable,    0x80
 
+.equ   vic_vect_addr,  0xfffff030
+
 #
 # the startup code
 #
@@ -49,6 +51,15 @@
 .arm
 
        # exception handling must go to the very beginning
+       #
+       # concerning irq:
+       #  - the ldr is at 0x18
+       #  - pc will be 0x18 + 8 at the moment of ldr (pipeline)
+       #  - substract 0xff0 => 0xfffff030
+       #  - that's the vectored address register
+       #  - the vic put in there the address of our service routine
+
+exception_vectors:
 
        ldr pc, handler_reset
        ldr pc, handler_undef_instruction
@@ -56,7 +67,8 @@
        ldr pc, handler_prefetch_abort
        ldr pc, handler_data_abort
        nop
-       ldr pc, handler_irq
+       ldr pc, [pc, #-0xff0]
+       #ldr pc, handler_irq
        ldr pc, handler_fiq
 
 handler_reset: .word handle_reset
@@ -64,7 +76,7 @@ handler_undef_instruction: .word interrupt_handler_undef_instruction
 handler_soft_ir: .word interrupt_handler_soft_ir
 handler_prefetch_abort: .word interrupt_handler_prefetch_abort
 handler_data_abort: .word interrupt_handler_data_abort
-handler_irq: .word interrupt_handler_irq
+handler_irq: .word vic_vect_addr
 handler_fiq: .word interrupt_handler_fiq
 
        # reset handling goes here
@@ -102,21 +114,41 @@ handle_reset:
        ldr r0, =stack_limit
        mov sl, r0
 
-       # copy data section
+       # enable irq and fiq
+       msr cpsr_c, #mode_system
+
+       # copy data section (only if we are in flash <=> _etext != _data)
 
        ldr r1, =_etext
        ldr r2, =_data
        ldr r3, =_edata
 
+       cmp r1, r2
+       beq copy_exception_vectors
+
 copy_data_loop:
 
        cmp r2, r3
        ldrlo r0, [r1], #4
        strlo r0, [r2], #4
        blo copy_data_loop
+       b start_of_c_code
+
+       # copy exception vectors (only if we are in ram <=> _etext = _data)
+
+copy_exception_vectors:
+
+       mov r0, #sram_addr
+       ldr r1, =exception_vectors
+       ldmia r1!, {r2-r9}
+       stmia r0!, {r2-r9}
+       ldmia r1!, {r2-r8}
+       stmia r0!, {r2-r8}
 
        # jump to c code
 
+start_of_c_code:
+
        adr lr, loop_forever
        mov r0, #0
        mov r1, #0