some hdw-tank stuff at gergos place ...

[my-code/atmel.git] / hdw-tank / main.asm

diff --git a/hdw-tank/main.asm b/hdw-tank/main.asm
new file mode 100644 (file)
index 0000000..e1ee14d
--- /dev/null
+++ b/hdw-tank/main.asm
@@ -0,0 +1,213 @@
+; main file of hdw-tank project
+;
+; author: hackbard@hackdaworld.org
+;
+
+; defines
+.define tmp    = r16
+
+; interrupts
+jmp RESET 
+jmp EXT_INT0 
+jmp EXT_INT1 
+jmp EXT_INT2 
+jmp EXT_INT3 
+jmp EXT_INT4 
+jmp EXT_INT5 
+jmp EXT_INT6 
+jmp EXT_INT7 
+jmp TIM2_COMP 
+jmp TIM2_OVF 
+jmp TIM1_CAPT 
+jmp TIM1_COMPA
+jmp TIM1_COMPB
+jmp TIM1_OVF 
+jmp TIM0_COMP 
+jmp TIM0_OVF 
+jmp SPI_STC 
+jmp USART0_RXC
+jmp USART0_DRE
+jmp USART0_TXC
+jmp ADC 
+jmp EE_RDY 
+jmp ANA_COMP 
+jmp TIM1_COMPC
+jmp TIM3_CAPT 
+jmp TIM3_COMPA
+jmp TIM3_COMPB
+jmp TIM3_COMPC
+jmp TIM3_OVF 
+jmp USART1_RXC
+jmp USART1_DRE
+jmp USART1_TXC
+jmp TWI 
+jmp SPM_RDY 
+
+; include subroutines
+.include "motor.asm"
+.include "uart.asm"
+
+RESET:
+INIT:
+
+       ; motor init
+       call 
+       ; uart init
+
+       ; set stackpointer
+       ldi r16, high(RAMEND)
+       out SPH,r16 
+       ldi r16, low(RAMEND)
+       out SPL,r16
+
+       ; global interrupt enable
+       sei 
+
+
+
+
+;
+; interrupt routines
+;
+
+EXT_INT0:
+       nop
+       reti
+
+EXT_INT1:
+       nop
+       reti
+
+EXT_INT2:
+       nop
+       reti
+
+EXT_INT3:
+       nop
+       reti
+
+EXT_INT4:
+       nop
+       reti
+
+EXT_INT5:
+       nop
+       reti
+
+EXT_INT6:
+       nop
+       reti
+
+EXT_INT7:
+       nop
+       reti
+
+TIM2_COMP:
+       nop
+       reti
+
+TIM2_OVF:
+       nop
+       reti
+
+TIM1_CAPT:
+       nop
+       reti
+
+TIM1_COMPA:
+       nop
+       reti
+
+TIM1_COMPB:
+       nop
+       reti
+
+TIM1_OVF:
+       nop
+       reti
+
+TIM0_COMP:
+       nop
+       reti
+
+TIM0_OVF:
+       nop
+       reti
+
+SPI_STC:
+       nop
+       reti
+
+USART0_RXC:
+
+       ; read received byte and drive the motor
+       ; in addition, loop it back to the host
+
+       in UDR
+
+       reti
+
+USART0_DRE:
+       nop
+       reti
+
+USART0_TXC:
+       nop
+       reti
+
+ADC:
+       nop
+       reti
+
+EE_RDY:
+       nop
+       reti
+
+ANA_COMP:
+       nop
+       reti
+
+TIM1_COMPC:
+       nop
+       reti
+
+TIM3_CAPT:
+       nop
+       reti
+
+TIM3_COMPA:
+       nop
+       reti
+
+TIM3_COMPB:
+       nop
+       reti
+
+TIM3_COMPC:
+       nop
+       reti
+
+TIM3_OVF:
+       nop
+       reti
+
+USART1_RXC:
+       nop
+       reti
+
+USART1_DRE:
+       nop
+       reti
+
+USART1_TXC:
+       nop
+       reti
+
+TWI:
+       nop
+       reti
+
+SPM_RDY:
+       nop
+       reti
+