init of new files (of hdw tank project + some small mods, more to come

[my-code/atmel.git] / led_plex / uart.asm

diff --git a/led_plex/uart.asm b/led_plex/uart.asm
new file mode 100644 (file)
index 0000000..e7a5830
--- /dev/null
+++ b/led_plex/uart.asm
@@ -0,0 +1,60 @@
+; uart functions
+
+; default uart settings / 19.2k @ 8 mhz
+; ifndef UART_BR_H
+.equ   UART_BR_H       = 0
+; ifndef UART_BR_L
+.equ   UART_BR_L       = 25
+
+UART_INIT:
+
+       ; baudrate
+       ldi tmp1,UART_BR_H
+       sts UBRR0H,tmp1
+       ldi tmp1,UART_BR_L
+       out UBRR0L,tmp1
+
+       ; enable
+       ldi tmp1,(1<<RXEN)|(1<<TXEN)
+       out UCSR0B,tmp1
+
+       ; frame format -> 8n1
+       ldi tmp1,(1<<UCSZ00)|(1<<UCSZ01)
+       sts UCSR0C,tmp1
+
+       ret
+
+UART_INT_RX_INIT:
+
+       in tmp1,UCSR0B
+       sbr tmp1,(1<<RXCIE0)
+       out UCSR0B,tmp1
+
+       ret
+
+UART_INT_TX_INIT:
+
+       in tmp1,UCSR0B
+       sbr tmp1,(1<<TXCIE0)
+       out UCSR0B,tmp1
+
+       ret
+
+UART_RX:
+
+       ; get/store received byte
+       sbis UCSR0A,RXC0
+               rjmp UART_RX
+       in uart_rxtx,UDR0
+
+       ret
+
+UART_TX:
+
+       ; transmit content of uart_rxtx
+       sbis UCSR0A,UDRE
+               rjmp UART_TX
+       out UDR0,uart_rxtx
+
+       ret
+