beginners/m128_tests.asm

   1 .include "../include/m128def.inc"
   2
   3 ; interrupt vectors
   4
   5 jmp RESET
   6
   7 reti
   8 nop
   9
  10 reti
  11 nop
  12
  13 reti
  14 nop
  15
  16 reti
  17 nop
  18
  19 jmp _INT4
  20
  21 jmp _INT5
  22
  23 jmp _INT6
  24
  25 jmp _INT7
  26
  27 reti
  28 nop
  29
  30 reti
  31 nop
  32
  33 reti
  34 nop
  35
  36 reti
  37 nop
  38
  39 reti
  40 nop
  41
  42 reti
  43 nop
  44
  45 reti
  46 nop
  47
  48 reti
  49 nop
  50
  51 reti
  52 nop
  53
  54 reti
  55 nop
  56
  57 reti
  58 nop
  59
  60 reti
  61 nop
  62
  63 reti
  64 nop
  65
  66 reti
  67 nop
  68
  69 reti
  70 nop
  71
  72 reti
  73 nop
  74
  75 reti
  76 nop
  77
  78 reti
  79 nop
  80
  81 reti
  82 nop
  83
  84 reti
  85 nop
  86
  87 reti
  88 nop
  89
  90 reti
  91 nop
  92
  93 reti
  94 nop
  95
  96 reti
  97 nop
  98
  99 reti
 100 nop
 101
 102 reti
 103 nop
 104
 105 RESET:
 106
 107         ; init
 108
 109         ; set stackpointer
 110         ldi r17,high(RAMEND)
 111         out SPH,r17
 112         ldi r17,low(RAMEND)
 113         out SPL,r17
 114
 115         ; uart
 116         ldi r17,(1<<TXEN0)
 117         out UCSR0B,r17
 118         ldi r17,(1<<UCSZ01|1<<UCSZ00)
 119         sts UCSR0C,r17
 120         ldi r17,0
 121         sts UBRR0H,r17
 122         ldi r17,25
 123         out UBRR0L,r17
 124
 125         ; switches
 126         ldi r17,(1<<PE4)|(1<<PE5)|(1<<PE6)|(1<<PE7)
 127         out PORTE,r17
 128         ldi r17,(1<<ISC41)|(1<<ISC51)|(1<<ISC61)|(1<<ISC71)
 129         out EICRB,r17
 130         ldi r17,(1<<INT4)|(1<<INT5)|(1<<INT6)|(1<<INT7)
 131         out EIMSK,r17
 132
 133         ; misc
 134         ldi r21,5
 135         ldi r18,0x34
 136
 137         ; enable interrupts
 138         sei
 139
 140 ; loop
 141
 142 MAIN:
 143
 144         UART_T:
 145                 sbis UCSR0A,UDRE0
 146                 rjmp UART_T
 147
 148         out UDR0,r18
 149
 150         rjmp MAIN
 151
 152 _INT4:
 153         inc r18
 154
 155         ldi r23,0
 156         WAIT_1:
 157                 ldi r24,0
 158                 WAIT_2:
 159                         ldi r25,0
 160                         WAIT_3:
 161                                 inc r25
 162                                 cpi r25,0xff
 163                                 brne WAIT_3
 164                         inc r24
 165                         cpi r24,0xff
 166                         brne WAIT_2
 167                 inc r23
 168                 cpi r23,0xff
 169                 brne WAIT_1
 170
 171         reti
 172
 173 _INT5:
 174         dec r18
 175         reti
 176
 177 _INT6:
 178         add r18,r21
 179         reti
 180
 181 _INT7:
 182         subi r18,5
 183         reti
 184