init of new files (of hdw tank project + some small mods, more to come
[my-code/atmel.git] / led_plex / uart.asm
1 ; uart functions
2
3 ; default uart settings / 19.2k @ 8 mhz
4 ; ifndef UART_BR_H
5 .equ    UART_BR_H       = 0
6 ; ifndef UART_BR_L
7 .equ    UART_BR_L       = 25
8
9 UART_INIT:
10
11         ; baudrate
12         ldi tmp1,UART_BR_H
13         sts UBRR0H,tmp1
14         ldi tmp1,UART_BR_L
15         out UBRR0L,tmp1
16
17         ; enable
18         ldi tmp1,(1<<RXEN)|(1<<TXEN)
19         out UCSR0B,tmp1
20
21         ; frame format -> 8n1
22         ldi tmp1,(1<<UCSZ00)|(1<<UCSZ01)
23         sts UCSR0C,tmp1
24
25         ret
26
27 UART_INT_RX_INIT:
28
29         in tmp1,UCSR0B
30         sbr tmp1,(1<<RXCIE0)
31         out UCSR0B,tmp1
32
33         ret
34
35 UART_INT_TX_INIT:
36
37         in tmp1,UCSR0B
38         sbr tmp1,(1<<TXCIE0)
39         out UCSR0B,tmp1
40
41         ret
42
43 UART_RX:
44
45         ; get/store received byte
46         sbis UCSR0A,RXC0
47                 rjmp UART_RX
48         in uart_rxtx,UDR0
49
50         ret
51
52 UART_TX:
53
54         ; transmit content of uart_rxtx
55         sbis UCSR0A,UDRE
56                 rjmp UART_TX
57         out UDR0,uart_rxtx
58
59         ret
60